Lines Matching +full:0 +full:xd000
35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
105 reg = <0x10600 0xA00>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
114 reg = <0x11000 0x24>;
116 #size-cells = <0>;
125 reg = <0x11080 0x24>;
127 #size-cells = <0>;
137 reg = <0x11500 0x40>;
142 reg = <0x12010 0x4>, <0x12210 0x4>;
143 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
152 reg = <0x12000 0x18>;
153 clocks = <&uartclk 0>;
164 reg = <0x12200 0x30>;
176 reg = <0x13000 0x100>;
177 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
184 reg = <0x18000 0x100>;
185 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
192 reg = <0x13200 0x100>;
200 reg = <0x13800 0x100>, <0x13C00 0x20>;
201 /* MPP1[19:0] */
204 gpio-ranges = <&pinctrl_nb 0 0 36>;
226 #clock-cells = <0>;
268 reg = <0x14000 0x60>;
273 reg = <0x18300 0x300>,
274 <0x1F000 0x400>,
275 <0x5C000 0x400>,
276 <0xe0178 0x8>;
282 #size-cells = <0>;
286 comphy0: phy@0 {
287 reg = <0>;
305 reg = <0x18800 0x100>, <0x18C00 0x20>;
306 /* MPP2[23:0] */
309 gpio-ranges = <&pinctrl_sb 0 0 30>;
349 reg = <0x30000 0x4000>;
357 #size-cells = <0>;
359 reg = <0x32004 0x4>;
364 reg = <0x40000 0x4000>;
373 reg = <0x58000 0x4000>;
377 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
384 reg = <0x5d000 0x800>;
386 #phy-cells = <0>;
392 reg = <0x5d800 0x800>;
397 reg = <0x5e000 0x1000>;
407 reg = <0x5f000 0x800>;
409 #phy-cells = <0>;
415 reg = <0x5f800 0x800>;
420 reg = <0x60900 0x100>,
421 <0x60b00 0x100>;
433 reg = <0x90000 0x20000>;
447 reg = <0xb0000 0x100>;
455 reg = <0xd0000 0x300>,
456 <0x1e808 0x4>;
458 clocks = <&nb_periph_clk 0>;
466 reg = <0xd8000 0x300>,
467 <0x17808 0x4>;
469 clocks = <&nb_periph_clk 0>;
476 reg = <0xe0000 0x178>;
479 phys = <&comphy2 0>;
488 reg = <0x1d00000 0x10000>, /* GICD */
489 <0x1d40000 0x40000>, /* GICR */
490 <0x1d80000 0x2000>, /* GICC */
491 <0x1d90000 0x2000>, /* GICH */
492 <0x1da0000 0x20000>; /* GICV */
501 reg = <0 0xd0070000 0 0x20000>;
504 bus-range = <0x00 0xff>;
511 * The 128 MiB address range [0xe8000000-0xf0000000] is
517 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
518 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
519 interrupt-map-mask = <0 0 0 7>;
520 interrupt-map = <0 0 0 1 &pcie_intc 0>,
521 <0 0 0 2 &pcie_intc 1>,
522 <0 0 0 3 &pcie_intc 2>,
523 <0 0 0 4 &pcie_intc 3>;
525 phys = <&comphy1 0>;
536 mboxes = <&rwtm 0>;