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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1232-revA.dts30 memory@0 {
32 reg = <0x0 0x0 0x0 0x80000000>;
42 flash@0 {
46 reg = <0x0>;
56 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
57 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
58 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
59 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
60 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
61 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts37 memory@0 {
39 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
93 #size-cells = <0>;
94 phy0: ethernet-phy@0 { /* VSC8211 */
95 reg = <0>;
111 reg = <0x20>;
119 reg = <0x68>;
150 ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
[all …]
H A Dzynqmp-zc1751-xm015-dc1.dts39 memory@0 {
41 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
100 pinctrl-0 = <&pinctrl_gem3_default>;
103 #size-cells = <0>;
104 phy0: ethernet-phy@0 {
105 reg = <0>;
113 pinctrl-0 = <&pinctrl_gpio_default>;
[all …]
H A Dzynqmp-sck-kv-g-revA.dtso33 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
36 si5332_0: si5332-0 { /* u17 */
38 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #size-cells = <0>;
77 pinctrl-0 = <&pinctrl_i2c1_default>;
[all …]
H A Dzynqmp-zcu104-revC.dts41 memory@0 {
43 reg = <0x0 0x0 0x0 0x80000000>;
48 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
73 pinctrl-0 = <&pinctrl_can1_default>;
117 pinctrl-0 = <&pinctrl_gem3_default>;
120 #size-cells = <0>;
124 reg = <0xc>;
[all …]
H A Dzynqmp-zcu104-revA.dts41 memory@0 {
43 reg = <0x0 0x0 0x0 0x80000000>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
68 pinctrl-0 = <&pinctrl_can1_default>;
112 pinctrl-0 = <&pinctrl_gem3_default>;
115 #size-cells = <0>;
119 reg = <0xc>;
120 ti,rx-internal-delay = <0x8>;
[all …]
H A Dzynqmp-zcu111-revA.dts42 memory@0 {
44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
71 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
75 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
79 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
83 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
87 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
91 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
95 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
99 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
[all …]
H A Dzynqmp-zcu102-revA.dts43 memory@0 {
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
[all …]
H A Dzynqmp-zcu106-revA.dts43 memory@0 {
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
34 #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
35 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
36 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
[all …]
H A Dvce_3_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
34 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
35 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
36 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dsoc.h9 #define SI_ENUM_BASE_DEFAULT 0x18000000
12 #define SICF_BIST_EN 0x8000
13 #define SICF_PME_EN 0x4000
14 #define SICF_CORE_BITS 0x3ffc
15 #define SICF_FGC 0x0002
16 #define SICF_CLOCK_EN 0x0001
19 #define SISF_BIST_DONE 0x8000
20 #define SISF_BIST_ERROR 0x4000
21 #define SISF_GATED_CLK 0x2000
22 #define SISF_DMA64 0x1000
[all …]
/linux/Documentation/devicetree/bindings/hwinfo/
H A Dloongson,ls2k-chipid.yaml36 reg = <0x1fe00000 0x3ffc>;
/linux/arch/arm/mach-omap1/
H A Dserial.h28 #define OMAP_UART_INFO_OFS 0x3ffc
31 #define OMAP7XX_PORT_SHIFT 0
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
[all …]
/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
H A Dspu_restore.c15 #define LS_SIZE 0x40000 /* 256K (in bytes) */
25 #define BR_INSTR 0x327fff80 /* br -4 */
26 #define NOP_INSTR 0x40200000 /* nop */
27 #define HEQ_INSTR 0x7b000000 /* heq $0, $0 */
28 #define STOP_INSTR 0x00000000 /* stop 0x0 */
29 #define ILLEGAL_INSTR 0x00800000 /* illegal instr */
30 #define RESTORE_COMPLETE 0x00003ffc /* stop 0x3ffc */
34 unsigned int ls = (unsigned int)&regs_spill[0]; in fetch_regs_from_mem()
36 unsigned int tag_id = 0; in fetch_regs_from_mem()
37 unsigned int cmd = 0x40; /* GET */ in fetch_regs_from_mem()
[all …]
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/linux/arch/powerpc/include/asm/
H A Dspu_csa.h23 #define SPU_SAVE_COMPLETE 0x3FFB
24 #define SPU_RESTORE_COMPLETE 0x3FFC
43 #define SPU_DECR_STATUS_RUNNING 0x1
44 #define SPU_DECR_STATUS_WRAPPED 0x2
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c18 #define SPMU_EVENT_TYPES_OFFSET 0x400
220 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in goya_coresight_timeout()
225 return 0; in goya_coresight_timeout()
243 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in goya_config_stm()
251 WREG32(base_reg + 0xE80, 0x80004); in goya_config_stm()
252 WREG32(base_reg + 0xD64, 7); in goya_config_stm()
253 WREG32(base_reg + 0xD60, 0); in goya_config_stm()
254 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in goya_config_stm()
255 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask)); in goya_config_stm()
256 WREG32(base_reg + 0xD60, 1); in goya_config_stm()
[all …]
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c17 #define SPMU_EVENT_TYPES_OFFSET 0x400
382 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", in gaudi_coresight_timeout()
387 return 0; in gaudi_coresight_timeout()
405 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); in gaudi_config_stm()
413 WREG32(base_reg + 0xE80, 0x80004); in gaudi_config_stm()
414 WREG32(base_reg + 0xD64, 7); in gaudi_config_stm()
415 WREG32(base_reg + 0xD60, 0); in gaudi_config_stm()
416 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); in gaudi_config_stm()
417 WREG32(base_reg + 0xD60, 1); in gaudi_config_stm()
418 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); in gaudi_config_stm()
[all …]
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c154 [GAUDI2_STM_PSOC_ARC0_CS] = 0,
155 [GAUDI2_STM_PSOC_ARC1_CS] = 0,
296 [GAUDI2_ETF_PSOC_ARC0_CS] = 0,
297 [GAUDI2_ETF_PSOC_ARC1_CS] = 0,
439 [GAUDI2_FUNNEL_PSOC_ARC0] = 0,
440 [GAUDI2_FUNNEL_PSOC_ARC1] = 0,
769 [GAUDI2_BMON_PSOC_ARC0_0] = 0,
770 [GAUDI2_BMON_PSOC_ARC0_1] = 0,
771 [GAUDI2_BMON_PSOC_ARC1_0] = 0,
772 [GAUDI2_BMON_PSOC_ARC1_1] = 0,
[all …]

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