Lines Matching +full:0 +full:x3ffc
43 memory@0 {
45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
145 #clock-cells = <0>;
151 #clock-cells = <0>;
171 pinctrl-0 = <&pinctrl_can1_default>;
215 pinctrl-0 = <&pinctrl_gem3_default>;
218 #size-cells = <0>;
221 reg = <0xc>;
223 ti,rx-internal-delay = <0x8>;
224 ti,tx-internal-delay = <0xa>;
225 ti,fifo-depth = <0x1>;
235 pinctrl-0 = <&pinctrl_gpio_default>;
246 pinctrl-0 = <&pinctrl_i2c0_default>;
253 reg = <0x20>;
259 * 0 - SFP_SI5328_INT_ALM
271 reg = <0x21>;
277 * 0 - VCCPSPLL_EN
298 #size-cells = <0>;
299 reg = <0x75>;
300 i2c@0 {
302 #size-cells = <0>;
303 reg = <0>;
309 reg = <0x40>;
316 reg = <0x41>;
323 reg = <0x42>;
330 reg = <0x43>;
337 reg = <0x44>;
344 reg = <0x45>;
351 reg = <0x46>;
358 reg = <0x47>;
365 reg = <0x4a>;
372 reg = <0x4b>;
378 #size-cells = <0>;
385 reg = <0x40>;
392 reg = <0x41>;
399 reg = <0x42>;
406 reg = <0x43>;
413 reg = <0x44>;
420 reg = <0x45>;
427 reg = <0x46>;
434 reg = <0x47>;
440 #size-cells = <0>;
445 reg = <0xa>;
449 reg = <0xb>;
453 reg = <0x10>;
457 reg = <0x13>;
461 reg = <0x14>;
465 reg = <0x15>;
469 reg = <0x16>;
473 reg = <0x17>;
477 reg = <0x18>;
481 reg = <0x1a>;
485 reg = <0x1b>;
489 reg = <0x1d>;
494 reg = <0x72>;
498 reg = <0x73>;
509 pinctrl-0 = <&pinctrl_i2c1_default>;
518 #size-cells = <0>;
519 reg = <0x74>;
520 i2c@0 {
522 #size-cells = <0>;
523 reg = <0>;
527 * 0 - 256B address 0x54
528 * 256B - 512B address 0x55
529 * 512B - 768B address 0x56
530 * 768B - 1024B address 0x57
534 reg = <0x54>;
539 #size-cells = <0>;
543 reg = <0x36>;
546 #size-cells = <0>;
551 si5341_0: out@0 {
553 reg = <0>;
586 #size-cells = <0>;
589 #clock-cells = <0>;
591 reg = <0x5d>;
600 #size-cells = <0>;
603 #clock-cells = <0>;
605 reg = <0x5d>;
614 #size-cells = <0>;
620 #size-cells = <0>;
624 reg = <0x4c>;
633 #size-cells = <0>;
634 reg = <0x75>;
636 i2c@0 {
638 #size-cells = <0>;
639 reg = <0>;
644 #size-cells = <0>;
650 #size-cells = <0>;
656 #size-cells = <0>;
662 #size-cells = <0>;
668 #size-cells = <0>;
674 #size-cells = <0>;
680 #size-cells = <0>;
682 /* SEP 0 */
956 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
962 flash@0 {
966 reg = <0x0>;
980 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
981 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
982 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
983 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
984 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
985 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
986 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
987 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
1000 pinctrl-0 = <&pinctrl_sdhci1_default>;
1007 pinctrl-0 = <&pinctrl_uart0_default>;
1013 pinctrl-0 = <&pinctrl_uart1_default>;
1020 pinctrl-0 = <&pinctrl_usb0_default>;
1022 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1043 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1044 <&psgtr 0 PHY_TYPE_DP 1 3>;