/linux/drivers/gpu/drm/i915/gvt/ |
H A D | display.c | 49 static int get_edp_pipe(struct intel_vgpu *vgpu) in get_edp_pipe() argument 51 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe() 69 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) in edp_pipe_is_enabled() argument 71 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled() 74 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled() 77 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled() 82 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled() argument 84 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled() 91 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled() 94 if (edp_pipe_is_enabled(vgpu) && in pipe_is_enabled() [all …]
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H A D | cfg_space.c | 69 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, in vgpu_pci_cfg_mem_write() argument 72 u8 *cfg_base = vgpu_cfg_space(vgpu); in vgpu_pci_cfg_mem_write() 97 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) { in vgpu_pci_cfg_mem_write() 98 pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off]) in vgpu_pci_cfg_mem_write() 101 vgpu->d3_entered = true; in vgpu_pci_cfg_mem_write() 103 vgpu->id, pwr); in vgpu_pci_cfg_mem_write() 117 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, in intel_vgpu_emulate_cfg_read() argument 120 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_cfg_read() 126 offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_read() 129 memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes); in intel_vgpu_emulate_cfg_read() [all …]
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H A D | gvt.h | 112 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) argument 125 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) argument 145 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 147 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 422 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) argument 423 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) argument 424 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) argument 425 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) argument 427 #define vgpu_aperture_pa_base(vgpu) \ argument [all …]
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H A D | aperture_gm.c | 42 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) in alloc_gm() argument 44 struct intel_gvt *gvt = vgpu->gvt; in alloc_gm() 52 node = &vgpu->gm.high_gm_node; in alloc_gm() 53 size = vgpu_hidden_sz(vgpu); in alloc_gm() 58 node = &vgpu->gm.low_gm_node; in alloc_gm() 59 size = vgpu_aperture_sz(vgpu); in alloc_gm() 80 static int alloc_vgpu_gm(struct intel_vgpu *vgpu) in alloc_vgpu_gm() argument 82 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_gm() 86 ret = alloc_gm(vgpu, false); in alloc_vgpu_gm() 90 ret = alloc_gm(vgpu, true); in alloc_vgpu_gm() [all …]
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H A D | edid.c | 54 static unsigned char edid_get_byte(struct intel_vgpu *vgpu) in edid_get_byte() argument 56 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid; in edid_get_byte() 73 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) { in edid_get_byte() 75 intel_vgpu_port(vgpu, edid->port)->edid; in edid_get_byte() 131 static void reset_gmbus_controller(struct intel_vgpu *vgpu) in reset_gmbus_controller() argument 133 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller() 134 if (!vgpu->display.i2c_edid.edid_available) in reset_gmbus_controller() 135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller() 136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE; in reset_gmbus_controller() 140 static int gmbus0_mmio_write(struct intel_vgpu *vgpu, in gmbus0_mmio_write() argument [all …]
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H A D | kvmgt.c | 71 size_t (*rw)(struct intel_vgpu *vgpu, char *buf, 73 void (*release)(struct intel_vgpu *vgpu, 97 struct intel_vgpu *vgpu; member 128 static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, in gvt_unpin_guest_page() argument 131 vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, in gvt_unpin_guest_page() 136 static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, in gvt_pin_guest_page() argument 152 ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, in gvt_pin_guest_page() 173 gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); in gvt_pin_guest_page() 177 static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, in gvt_dma_map_page() argument 180 struct device *dev = vgpu->gvt->gt->i915->drm.dev; in gvt_dma_map_page() [all …]
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H A D | sched_policy.c | 37 static bool vgpu_has_pending_workload(struct intel_vgpu *vgpu) in vgpu_has_pending_workload() argument 42 for_each_engine(engine, vgpu->gvt->gt, i) { in vgpu_has_pending_workload() 43 if (!list_empty(workload_q_head(vgpu, engine))) in vgpu_has_pending_workload() 55 struct intel_vgpu *vgpu; member 75 static void vgpu_update_timeslice(struct intel_vgpu *vgpu, ktime_t cur_time) in vgpu_update_timeslice() argument 80 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice() 83 vgpu_data = vgpu->sched_data; in vgpu_update_timeslice() 179 struct intel_vgpu *vgpu = NULL; in find_busy_vgpu() local 187 if (!vgpu_has_pending_workload(vgpu_data->vgpu)) in find_busy_vgpu() 192 vgpu = vgpu_data->vgpu; in find_busy_vgpu() [all …]
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H A D | handlers.c | 96 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, in read_vreg() argument 99 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg() 102 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, in write_vreg() argument 105 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg() 182 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) in enter_failsafe_mode() argument 197 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); in enter_failsafe_mode() 198 vgpu->failsafe = true; in enter_failsafe_mode() 201 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, in sanitize_fence_mmio_access() argument 204 unsigned int max_fence = vgpu_fence_sz(vgpu); in sanitize_fence_mmio_access() 214 if (!vgpu->pv_notified) in sanitize_fence_mmio_access() [all …]
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H A D | interrupt.c | 70 static void update_upstream_irq(struct intel_vgpu *vgpu, 194 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, in intel_vgpu_reg_imr_handler() argument 197 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler() 201 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler() 202 (vgpu_vreg(vgpu, reg) ^ imr)); in intel_vgpu_reg_imr_handler() 204 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler() 206 ops->check_pending_irq(vgpu); in intel_vgpu_reg_imr_handler() 224 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, in intel_vgpu_reg_master_irq_handler() argument 227 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler() 230 u32 virtual_ier = vgpu_vreg(vgpu, reg); in intel_vgpu_reg_master_irq_handler() [all …]
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H A D | execlist.c | 93 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_execlist_status() local 98 status.ldw = vgpu_vreg(vgpu, status_reg); in emulate_execlist_status() 99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status() 117 vgpu_vreg(vgpu, status_reg) = status.ldw; in emulate_execlist_status() 118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status() 121 vgpu->id, status_reg, status.ldw, status.udw); in emulate_execlist_status() 128 struct intel_vgpu *vgpu = execlist->vgpu; in emulate_csb_update() local 139 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); in emulate_csb_update() 152 vgpu_vreg(vgpu, offset) = status->ldw; in emulate_csb_update() 153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update() [all …]
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H A D | debugfs.c | 29 struct intel_vgpu *vgpu; member 66 vreg = vgpu_vreg(param->vgpu, offset); in mmio_diff_handler() 86 struct intel_vgpu *vgpu = s->private; in vgpu_mmio_diff_show() local 87 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show() 89 .vgpu = vgpu, in vgpu_mmio_diff_show() 129 struct intel_vgpu *vgpu = (struct intel_vgpu *)data; in vgpu_scan_nonprivbb_get() local 131 *val = vgpu->scan_nonprivbb; in vgpu_scan_nonprivbb_get() 144 struct intel_vgpu *vgpu = (struct intel_vgpu *)data; in vgpu_scan_nonprivbb_set() local 146 vgpu->scan_nonprivbb = val; in vgpu_scan_nonprivbb_set() 156 struct intel_vgpu *vgpu = (struct intel_vgpu *)data; in vgpu_status_get() local [all …]
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H A D | dmabuf.c | 49 struct intel_vgpu *vgpu; in vgpu_gem_get_pages() local 65 vgpu = fb_info->obj->vgpu; in vgpu_gem_get_pages() 66 if (drm_WARN_ON(&dev_priv->drm, !vgpu)) in vgpu_gem_get_pages() 83 if (intel_gvt_dma_pin_guest_page(vgpu, dma_addr)) { in vgpu_gem_get_pages() 102 intel_gvt_dma_unmap_guest_page(vgpu, dma_addr); in vgpu_gem_get_pages() 120 struct intel_vgpu *vgpu = obj->vgpu; in vgpu_gem_put_pages() local 124 intel_gvt_dma_unmap_guest_page(vgpu, in vgpu_gem_put_pages() 136 struct intel_vgpu *vgpu = obj->vgpu; in dmabuf_gem_object_free() local 140 if (vgpu && test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status) && in dmabuf_gem_object_free() 141 !list_empty(&vgpu->dmabuf_obj_list_head)) { in dmabuf_gem_object_free() [all …]
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H A D | fb_decoder.c | 153 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, in intel_vgpu_get_stride() argument 156 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_get_stride() 159 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask; in intel_vgpu_get_stride() 190 static int get_active_pipe(struct intel_vgpu *vgpu) in get_active_pipe() argument 195 if (pipe_is_enabled(vgpu, i)) in get_active_pipe() 210 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, in intel_vgpu_decode_primary_plane() argument 213 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_decode_primary_plane() 218 pipe = get_active_pipe(vgpu); in intel_vgpu_decode_primary_plane() 222 val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)); in intel_vgpu_decode_primary_plane() 256 plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane() [all …]
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H A D | gtt.h | 63 struct intel_vgpu *vgpu); 69 struct intel_vgpu *vgpu); 151 struct intel_vgpu *vgpu; member 182 struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu, 218 int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); 219 void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); 220 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); 221 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); 226 struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, 243 struct intel_vgpu *vgpu; member [all …]
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H A D | sched_policy.h | 43 int (*init_vgpu)(struct intel_vgpu *vgpu); 44 void (*clean_vgpu)(struct intel_vgpu *vgpu); 45 void (*start_schedule)(struct intel_vgpu *vgpu); 46 void (*stop_schedule)(struct intel_vgpu *vgpu); 55 int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu); 57 void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu); 59 void intel_vgpu_start_schedule(struct intel_vgpu *vgpu); 61 void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu);
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H A D | mmio.h | 83 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu); 84 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr); 85 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu); 87 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa); 89 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, 91 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, 94 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 96 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 102 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 105 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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H A D | scheduler.h | 86 struct intel_vgpu *vgpu; member 134 #define workload_q_head(vgpu, e) \ argument 135 (&(vgpu)->submission.workload_q_head[(e)->id]) 143 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu); 145 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu); 147 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, 150 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu); 152 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, 160 intel_vgpu_create_workload(struct intel_vgpu *vgpu, 166 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
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H A D | opregion.c | 220 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) in intel_vgpu_init_opregion() argument 227 gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); in intel_vgpu_init_opregion() 228 vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL | in intel_vgpu_init_opregion() 231 if (!vgpu_opregion(vgpu)->va) { in intel_vgpu_init_opregion() 237 buf = (u8 *)vgpu_opregion(vgpu)->va; in intel_vgpu_init_opregion() 267 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) in intel_vgpu_opregion_base_write_handler() argument 275 vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; in intel_vgpu_opregion_base_write_handler() 284 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) in intel_vgpu_clean_opregion() argument 286 gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); in intel_vgpu_clean_opregion() 288 if (!vgpu_opregion(vgpu)->va) in intel_vgpu_clean_opregion() [all …]
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H A D | cmd_parser.c | 479 struct intel_vgpu *vgpu; member 520 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) 738 s->vgpu->id, s->engine->name, in parser_exec_state_dump() 861 struct intel_vgpu *vgpu = s->vgpu; in cmd_pdp_mmio_update_handler() local 871 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps); in cmd_pdp_mmio_update_handler() 895 struct intel_vgpu *vgpu = s->vgpu; in cmd_reg_handler() local 896 struct intel_gvt *gvt = vgpu->gvt; in cmd_reg_handler() 955 vreg = &vgpu_vreg(s->vgpu, offset); in cmd_reg_handler() 986 ret = mmio_info->write(s->vgpu, offset, in cmd_reg_handler() 1017 intel_gvt_read_gpa(s->vgpu, in cmd_reg_handler() [all …]
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H A D | page_track.h | 45 struct intel_vgpu *vgpu, unsigned long gfn); 47 int intel_vgpu_register_page_track(struct intel_vgpu *vgpu, 50 void intel_vgpu_unregister_page_track(struct intel_vgpu *vgpu, 53 int intel_vgpu_enable_page_track(struct intel_vgpu *vgpu, unsigned long gfn); 54 int intel_vgpu_disable_page_track(struct intel_vgpu *vgpu, unsigned long gfn); 56 int intel_vgpu_page_track_handler(struct intel_vgpu *vgpu, u64 gpa,
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H A D | interrupt.h | 145 enum intel_gvt_event_type event, struct intel_vgpu *vgpu); 149 void (*check_pending_irq)(struct intel_vgpu *vgpu); 195 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 198 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 200 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 202 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 204 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
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H A D | mmio_context.c | 209 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, in restore_context_mmio_for_inhibit() argument 215 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit() 237 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit() 239 *(cs-2), *(cs-1), vgpu->id, ring_id); in restore_context_mmio_for_inhibit() 253 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, in restore_render_mocs_control_for_inhibit() argument 267 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit() 269 *(cs-2), *(cs-1), vgpu->id, req->engine->id); in restore_render_mocs_control_for_inhibit() 280 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, in restore_render_mocs_l3cc_for_inhibit() argument 294 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit() 296 *(cs-2), *(cs-1), vgpu->id, req->engine->id); in restore_render_mocs_l3cc_for_inhibit() [all …]
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H A D | dmabuf.h | 55 struct intel_vgpu *vgpu; member 63 int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args); 64 int intel_vgpu_get_dmabuf(struct intel_vgpu *vgpu, unsigned int dmabuf_id); 65 void intel_vgpu_dmabuf_cleanup(struct intel_vgpu *vgpu);
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H A D | edid.h | 133 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu); 135 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, 138 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu, 141 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
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/linux/drivers/gpu/drm/i915/ |
H A D | intel_gvt.c | 72 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; in free_initial_hw_state() local 74 vfree(vgpu->initial_mmio); in free_initial_hw_state() 75 vgpu->initial_mmio = NULL; in free_initial_hw_state() 77 kfree(vgpu->initial_cfg_space); in free_initial_hw_state() 78 vgpu->initial_cfg_space = NULL; in free_initial_hw_state() 107 struct i915_virtual_gpu *vgpu = &dev_priv->vgpu; in save_initial_hw_state() local 116 vgpu->initial_cfg_space = mem; in save_initial_hw_state() 127 vgpu->initial_mmio = mem; in save_initial_hw_state() 130 iter.data = vgpu->initial_mmio; in save_initial_hw_state() 140 vfree(vgpu->initial_mmio); in save_initial_hw_state() [all …]
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