Lines Matching refs:vgpu
51 static int get_edp_pipe(struct intel_vgpu *vgpu)
53 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
71 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
73 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
76 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
79 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
84 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
86 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
93 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE)
96 if (edp_pipe_is_enabled(vgpu) &&
97 get_edp_pipe(vgpu) == pipe)
185 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
187 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
196 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
202 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &=
204 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
205 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
206 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
207 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
211 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &=
215 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
220 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
222 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
226 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
231 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
234 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
236 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
238 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
240 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
242 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
243 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
244 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
246 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
249 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
251 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
252 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
254 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
255 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
263 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
264 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
272 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
273 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
274 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
275 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
276 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
279 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
280 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
281 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
283 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
290 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
296 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
298 vgpu_vreg_t(vgpu,
302 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
304 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
308 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
309 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
310 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
311 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
313 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
320 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
328 vgpu_vreg_t(vgpu,
333 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
335 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
339 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
340 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
341 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
342 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
344 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
346 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
348 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
351 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
355 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
357 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
359 vgpu_vreg_t(vgpu,
364 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
366 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
373 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
381 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
383 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
396 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
398 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
400 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
402 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
409 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64);
410 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e;
411 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000;
412 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e;
413 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000;
416 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
417 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
419 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
421 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
423 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
424 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
427 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
432 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
434 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
437 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
438 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
439 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
442 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
443 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
445 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
447 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
449 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
450 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
453 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
458 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
460 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
463 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
464 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
465 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
468 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
469 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
471 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
473 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
475 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
476 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &=
479 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |=
484 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
486 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
489 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
491 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
498 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
499 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
502 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
504 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
507 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
509 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
514 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
518 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;
519 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
520 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK;
521 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE;
524 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE;
527 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
529 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
541 struct intel_vgpu *vgpu;
544 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
547 intel_gvt_request_service(vgpu->gvt,
548 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
553 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
556 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
557 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
558 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
583 vgpu->display.port_num = port_num;
590 emulate_monitor_status_change(vgpu);
597 * @vgpu: vGPU operated
605 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
607 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
609 intel_vgpu_port(vgpu, vgpu->display.port_num);
636 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
638 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
640 struct intel_vgpu_irq *irq = &vgpu->irq;
654 if (!pipe_is_enabled(vgpu, pipe))
657 intel_vgpu_trigger_virtual_event(vgpu, event);
660 if (pipe_is_enabled(vgpu, pipe)) {
661 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++;
662 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
666 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
668 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
672 mutex_lock(&vgpu->vgpu_lock);
674 emulate_vblank_on_pipe(vgpu, pipe);
675 mutex_unlock(&vgpu->vgpu_lock);
680 * @vgpu: a vGPU
686 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
688 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
696 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
698 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
700 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
702 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
704 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
705 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
707 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
709 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
711 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
714 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
719 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
721 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
723 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
725 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
727 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
729 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
732 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
734 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
739 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
741 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
743 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
745 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
747 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
749 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
752 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
754 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
757 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
759 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
761 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
763 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
770 * @vgpu: a vGPU
775 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
777 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
783 clean_virtual_dp_monitor(vgpu, PORT_D);
785 clean_virtual_dp_monitor(vgpu, PORT_B);
787 vgpu_update_vblank_emulation(vgpu, false);
792 * @vgpu: a vGPU
801 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
803 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
805 intel_vgpu_init_i2c_edid(vgpu);
811 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
814 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
820 * @vgpu: a vGPU
825 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
827 emulate_monitor_status_change(vgpu);