1be1da707SZhi Wang /*
2be1da707SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3be1da707SZhi Wang *
4be1da707SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a
5be1da707SZhi Wang * copy of this software and associated documentation files (the "Software"),
6be1da707SZhi Wang * to deal in the Software without restriction, including without limitation
7be1da707SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8be1da707SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the
9be1da707SZhi Wang * Software is furnished to do so, subject to the following conditions:
10be1da707SZhi Wang *
11be1da707SZhi Wang * The above copyright notice and this permission notice (including the next
12be1da707SZhi Wang * paragraph) shall be included in all copies or substantial portions of the
13be1da707SZhi Wang * Software.
14be1da707SZhi Wang *
15be1da707SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16be1da707SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17be1da707SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18be1da707SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19be1da707SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20be1da707SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21be1da707SZhi Wang * SOFTWARE.
22be1da707SZhi Wang *
23be1da707SZhi Wang * Authors:
24be1da707SZhi Wang * Ke Yu
25be1da707SZhi Wang * Kevin Tian <kevin.tian@intel.com>
26be1da707SZhi Wang * Zhiyuan Lv <zhiyuan.lv@intel.com>
27be1da707SZhi Wang *
28be1da707SZhi Wang * Contributors:
29be1da707SZhi Wang * Min He <min.he@intel.com>
30be1da707SZhi Wang * Ping Gao <ping.a.gao@intel.com>
31be1da707SZhi Wang * Tina Zhang <tina.zhang@intel.com>
32be1da707SZhi Wang * Yulei Zhang <yulei.zhang@intel.com>
33be1da707SZhi Wang * Zhi Wang <zhi.a.wang@intel.com>
34be1da707SZhi Wang *
35be1da707SZhi Wang */
36be1da707SZhi Wang
37be1da707SZhi Wang #include <linux/slab.h>
382871ea85SChris Wilson
39be1da707SZhi Wang #include "i915_drv.h"
40801543b2SJani Nikula #include "i915_reg.h"
41202b1f4cSMatt Roper #include "gt/intel_engine_regs.h"
4245233ab2SChris Wilson #include "gt/intel_gpu_commands.h"
430d6419e9SMatt Roper #include "gt/intel_gt_regs.h"
44493f30cdSYan Zhao #include "gt/intel_lrc.h"
452871ea85SChris Wilson #include "gt/intel_ring.h"
46493f30cdSYan Zhao #include "gt/intel_gt_requests.h"
4797ea6565SChris Wilson #include "gt/shmem_utils.h"
48feddf6e8SZhenyu Wang #include "gvt.h"
49feddf6e8SZhenyu Wang #include "i915_pvinfo.h"
50be1da707SZhi Wang #include "trace.h"
51be1da707SZhi Wang
52514ca6dfSVille Syrjälä #include "display/i9xx_plane_regs.h"
53acc855d3SJani Nikula #include "display/intel_display.h"
5441b088a2SJani Nikula #include "display/intel_sprite_regs.h"
55493f30cdSYan Zhao #include "gem/i915_gem_context.h"
56493f30cdSYan Zhao #include "gem/i915_gem_pm.h"
57493f30cdSYan Zhao #include "gt/intel_context.h"
58493f30cdSYan Zhao
59be1da707SZhi Wang #define INVALID_OP (~0U)
60be1da707SZhi Wang
61be1da707SZhi Wang #define OP_LEN_MI 9
62be1da707SZhi Wang #define OP_LEN_2D 10
63be1da707SZhi Wang #define OP_LEN_3D_MEDIA 16
64be1da707SZhi Wang #define OP_LEN_MFX_VC 16
65be1da707SZhi Wang #define OP_LEN_VEBOX 16
66be1da707SZhi Wang
67be1da707SZhi Wang #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
68be1da707SZhi Wang
69be1da707SZhi Wang struct sub_op_bits {
70be1da707SZhi Wang int hi;
71be1da707SZhi Wang int low;
72be1da707SZhi Wang };
73be1da707SZhi Wang struct decode_info {
74ed8cce30SJani Nikula const char *name;
75be1da707SZhi Wang int op_len;
76be1da707SZhi Wang int nr_sub_op;
77ed8cce30SJani Nikula const struct sub_op_bits *sub_op;
78be1da707SZhi Wang };
79be1da707SZhi Wang
80be1da707SZhi Wang #define MAX_CMD_BUDGET 0x7fffffff
81be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
82be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
83be1da707SZhi Wang #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
84be1da707SZhi Wang
85be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
86be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
87be1da707SZhi Wang #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
88be1da707SZhi Wang
89be1da707SZhi Wang /* Render Command Map */
90be1da707SZhi Wang
91be1da707SZhi Wang /* MI_* command Opcode (28:23) */
92be1da707SZhi Wang #define OP_MI_NOOP 0x0
93be1da707SZhi Wang #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
94be1da707SZhi Wang #define OP_MI_USER_INTERRUPT 0x2
95be1da707SZhi Wang #define OP_MI_WAIT_FOR_EVENT 0x3
96be1da707SZhi Wang #define OP_MI_FLUSH 0x4
97be1da707SZhi Wang #define OP_MI_ARB_CHECK 0x5
98be1da707SZhi Wang #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
99be1da707SZhi Wang #define OP_MI_REPORT_HEAD 0x7
100be1da707SZhi Wang #define OP_MI_ARB_ON_OFF 0x8
101be1da707SZhi Wang #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
102be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_END 0xA
103be1da707SZhi Wang #define OP_MI_SUSPEND_FLUSH 0xB
104be1da707SZhi Wang #define OP_MI_PREDICATE 0xC /* IVB+ */
105be1da707SZhi Wang #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
106be1da707SZhi Wang #define OP_MI_SET_APPID 0xE /* IVB+ */
107be1da707SZhi Wang #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
108be1da707SZhi Wang #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
109be1da707SZhi Wang #define OP_MI_DISPLAY_FLIP 0x14
110be1da707SZhi Wang #define OP_MI_SEMAPHORE_MBOX 0x16
111be1da707SZhi Wang #define OP_MI_SET_CONTEXT 0x18
112be1da707SZhi Wang #define OP_MI_MATH 0x1A
113be1da707SZhi Wang #define OP_MI_URB_CLEAR 0x19
114be1da707SZhi Wang #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
115be1da707SZhi Wang #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
116be1da707SZhi Wang
117be1da707SZhi Wang #define OP_MI_STORE_DATA_IMM 0x20
118be1da707SZhi Wang #define OP_MI_STORE_DATA_INDEX 0x21
119be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_IMM 0x22
120be1da707SZhi Wang #define OP_MI_UPDATE_GTT 0x23
121be1da707SZhi Wang #define OP_MI_STORE_REGISTER_MEM 0x24
122be1da707SZhi Wang #define OP_MI_FLUSH_DW 0x26
123be1da707SZhi Wang #define OP_MI_CLFLUSH 0x27
124be1da707SZhi Wang #define OP_MI_REPORT_PERF_COUNT 0x28
125be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
126be1da707SZhi Wang #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
127be1da707SZhi Wang #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
128be1da707SZhi Wang #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
129be1da707SZhi Wang #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
130be1da707SZhi Wang #define OP_MI_2E 0x2E /* BDW+ */
131be1da707SZhi Wang #define OP_MI_2F 0x2F /* BDW+ */
132be1da707SZhi Wang #define OP_MI_BATCH_BUFFER_START 0x31
133be1da707SZhi Wang
134be1da707SZhi Wang /* Bit definition for dword 0 */
135be1da707SZhi Wang #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
136be1da707SZhi Wang
137be1da707SZhi Wang #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
138be1da707SZhi Wang
139be1da707SZhi Wang #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
140be1da707SZhi Wang #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
141be1da707SZhi Wang #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
142be1da707SZhi Wang #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
143be1da707SZhi Wang
144be1da707SZhi Wang /* 2D command: Opcode (28:22) */
145be1da707SZhi Wang #define OP_2D(x) ((2<<7) | x)
146be1da707SZhi Wang
147be1da707SZhi Wang #define OP_XY_SETUP_BLT OP_2D(0x1)
148be1da707SZhi Wang #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
149be1da707SZhi Wang #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
150be1da707SZhi Wang #define OP_XY_PIXEL_BLT OP_2D(0x24)
151be1da707SZhi Wang #define OP_XY_SCANLINES_BLT OP_2D(0x25)
152be1da707SZhi Wang #define OP_XY_TEXT_BLT OP_2D(0x26)
153be1da707SZhi Wang #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
154be1da707SZhi Wang #define OP_XY_COLOR_BLT OP_2D(0x50)
155be1da707SZhi Wang #define OP_XY_PAT_BLT OP_2D(0x51)
156be1da707SZhi Wang #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
157be1da707SZhi Wang #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
158be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
159be1da707SZhi Wang #define OP_XY_FULL_BLT OP_2D(0x55)
160be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
161be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
162be1da707SZhi Wang #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
163be1da707SZhi Wang #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
164be1da707SZhi Wang #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
165be1da707SZhi Wang #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
166be1da707SZhi Wang #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
167be1da707SZhi Wang #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
168be1da707SZhi Wang #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
169be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
170be1da707SZhi Wang #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
171be1da707SZhi Wang
172be1da707SZhi Wang /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
173be1da707SZhi Wang #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
174be1da707SZhi Wang ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
175be1da707SZhi Wang
176be1da707SZhi Wang #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
177be1da707SZhi Wang
178be1da707SZhi Wang #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
179be1da707SZhi Wang #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
180be1da707SZhi Wang #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
1812484b172SYan Zhao #define OP_SWTESS_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x03)
182be1da707SZhi Wang
183be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
184be1da707SZhi Wang
185be1da707SZhi Wang #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
186be1da707SZhi Wang
187be1da707SZhi Wang #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
188be1da707SZhi Wang #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
189be1da707SZhi Wang #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
190be1da707SZhi Wang #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
191be1da707SZhi Wang #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
19202b966c1SColin Xu #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
193be1da707SZhi Wang
194be1da707SZhi Wang #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
195be1da707SZhi Wang #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
196be1da707SZhi Wang #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
197be1da707SZhi Wang #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
198be1da707SZhi Wang
199be1da707SZhi Wang #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
200be1da707SZhi Wang #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
201be1da707SZhi Wang #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
202be1da707SZhi Wang #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
203be1da707SZhi Wang #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
204be1da707SZhi Wang #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
205be1da707SZhi Wang #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
206be1da707SZhi Wang #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
207be1da707SZhi Wang #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
208be1da707SZhi Wang #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
209be1da707SZhi Wang #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
210be1da707SZhi Wang #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
211be1da707SZhi Wang #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
212be1da707SZhi Wang #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
213be1da707SZhi Wang #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
214be1da707SZhi Wang #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
215be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
216be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
217be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
218be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
219be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
220be1da707SZhi Wang #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
221be1da707SZhi Wang #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
222be1da707SZhi Wang #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
223be1da707SZhi Wang #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
224be1da707SZhi Wang #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
225be1da707SZhi Wang #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
226be1da707SZhi Wang #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
227be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
228be1da707SZhi Wang #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
229be1da707SZhi Wang #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
230be1da707SZhi Wang #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
231be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
232be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
233be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
234be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
235be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
236be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
237be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
238be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
239be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
240be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
241be1da707SZhi Wang #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
242be1da707SZhi Wang #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
243be1da707SZhi Wang #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
244be1da707SZhi Wang #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
245be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
246be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
247be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
248be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
249be1da707SZhi Wang #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
250be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
251be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
252be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
253be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
254be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
255be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
256be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
257be1da707SZhi Wang #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
258be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
259be1da707SZhi Wang #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
260be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
261be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
262be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
263be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
264be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
265be1da707SZhi Wang
266be1da707SZhi Wang #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
267be1da707SZhi Wang #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
268be1da707SZhi Wang #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
269be1da707SZhi Wang #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
270be1da707SZhi Wang #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
271be1da707SZhi Wang #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
272be1da707SZhi Wang #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
273be1da707SZhi Wang #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
274be1da707SZhi Wang #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
275be1da707SZhi Wang #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
276be1da707SZhi Wang #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
277be1da707SZhi Wang
278be1da707SZhi Wang #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
279be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
280be1da707SZhi Wang #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
281be1da707SZhi Wang #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
282be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
283be1da707SZhi Wang #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
284be1da707SZhi Wang #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
285be1da707SZhi Wang #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
286be1da707SZhi Wang #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
287be1da707SZhi Wang #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
288be1da707SZhi Wang #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
289be1da707SZhi Wang #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
290be1da707SZhi Wang #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
291be1da707SZhi Wang #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
292be1da707SZhi Wang #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
293be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
294be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
295be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
296be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
297be1da707SZhi Wang #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
298be1da707SZhi Wang #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
299be1da707SZhi Wang #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
300be1da707SZhi Wang #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
301be1da707SZhi Wang #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
302be1da707SZhi Wang #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
303be1da707SZhi Wang #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
304be1da707SZhi Wang #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
305be1da707SZhi Wang #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
306be1da707SZhi Wang
307be1da707SZhi Wang /* VCCP Command Parser */
308be1da707SZhi Wang
309be1da707SZhi Wang /*
310be1da707SZhi Wang * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
311be1da707SZhi Wang * git://anongit.freedesktop.org/vaapi/intel-driver
312be1da707SZhi Wang * src/i965_defines.h
313be1da707SZhi Wang *
314be1da707SZhi Wang */
315be1da707SZhi Wang
316be1da707SZhi Wang #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
317be1da707SZhi Wang (3 << 13 | \
318be1da707SZhi Wang (pipeline) << 11 | \
319be1da707SZhi Wang (op) << 8 | \
320be1da707SZhi Wang (sub_opa) << 5 | \
321be1da707SZhi Wang (sub_opb))
322be1da707SZhi Wang
323be1da707SZhi Wang #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
324be1da707SZhi Wang #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
325be1da707SZhi Wang #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
326be1da707SZhi Wang #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
327be1da707SZhi Wang #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
328be1da707SZhi Wang #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
329be1da707SZhi Wang #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
330be1da707SZhi Wang #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
331be1da707SZhi Wang #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
332be1da707SZhi Wang #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
333be1da707SZhi Wang #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
334be1da707SZhi Wang
335be1da707SZhi Wang #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
336be1da707SZhi Wang
337be1da707SZhi Wang #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
338be1da707SZhi Wang #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
339be1da707SZhi Wang #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
340be1da707SZhi Wang #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
341be1da707SZhi Wang #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
342be1da707SZhi Wang #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
343be1da707SZhi Wang #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
344be1da707SZhi Wang #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
345be1da707SZhi Wang #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
346be1da707SZhi Wang #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
347be1da707SZhi Wang #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
348be1da707SZhi Wang #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
349be1da707SZhi Wang
350be1da707SZhi Wang #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
351be1da707SZhi Wang #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
352be1da707SZhi Wang #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
353be1da707SZhi Wang #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
354be1da707SZhi Wang #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
355be1da707SZhi Wang
356be1da707SZhi Wang #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
357be1da707SZhi Wang #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
358be1da707SZhi Wang #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
359be1da707SZhi Wang #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
360be1da707SZhi Wang #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
361be1da707SZhi Wang
362be1da707SZhi Wang #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
363be1da707SZhi Wang #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
364be1da707SZhi Wang #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
365be1da707SZhi Wang
366be1da707SZhi Wang #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
367be1da707SZhi Wang #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
368be1da707SZhi Wang #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
369be1da707SZhi Wang
370be1da707SZhi Wang #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
371be1da707SZhi Wang (3 << 13 | \
372be1da707SZhi Wang (pipeline) << 11 | \
373be1da707SZhi Wang (op) << 8 | \
374be1da707SZhi Wang (sub_opa) << 5 | \
375be1da707SZhi Wang (sub_opb))
376be1da707SZhi Wang
377be1da707SZhi Wang #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
378be1da707SZhi Wang #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
379be1da707SZhi Wang #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
380be1da707SZhi Wang
381be1da707SZhi Wang struct parser_exec_state;
382be1da707SZhi Wang
383be1da707SZhi Wang typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
384be1da707SZhi Wang
385be1da707SZhi Wang #define GVT_CMD_HASH_BITS 7
386be1da707SZhi Wang
387be1da707SZhi Wang /* which DWords need address fix */
388be1da707SZhi Wang #define ADDR_FIX_1(x1) (1 << (x1))
389be1da707SZhi Wang #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
390be1da707SZhi Wang #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
391be1da707SZhi Wang #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
392be1da707SZhi Wang #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
393be1da707SZhi Wang
39400a33be4SGao, Fred #define DWORD_FIELD(dword, end, start) \
39500a33be4SGao, Fred FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
39600a33be4SGao, Fred
3971e2adc0dSGao, Fred #define OP_LENGTH_BIAS 2
3981e2adc0dSGao, Fred #define CMD_LEN(value) (value + OP_LENGTH_BIAS)
3991e2adc0dSGao, Fred
gvt_check_valid_cmd_length(int len,int valid_len)4001e2adc0dSGao, Fred static int gvt_check_valid_cmd_length(int len, int valid_len)
4011e2adc0dSGao, Fred {
4021e2adc0dSGao, Fred if (valid_len != len) {
4031e2adc0dSGao, Fred gvt_err("len is not valid: len=%u valid_len=%u\n",
4041e2adc0dSGao, Fred len, valid_len);
4051e2adc0dSGao, Fred return -EFAULT;
4061e2adc0dSGao, Fred }
4071e2adc0dSGao, Fred return 0;
4081e2adc0dSGao, Fred }
4091e2adc0dSGao, Fred
410be1da707SZhi Wang struct cmd_info {
411b007065aSJani Nikula const char *name;
412be1da707SZhi Wang u32 opcode;
413be1da707SZhi Wang
4144f870f1fSGao, Fred #define F_LEN_MASK 3U
415be1da707SZhi Wang #define F_LEN_CONST 1U
416be1da707SZhi Wang #define F_LEN_VAR 0U
4174f870f1fSGao, Fred /* value is const although LEN maybe variable */
4184f870f1fSGao, Fred #define F_LEN_VAR_FIXED (1<<1)
419be1da707SZhi Wang
420be1da707SZhi Wang /*
421be1da707SZhi Wang * command has its own ip advance logic
422be1da707SZhi Wang * e.g. MI_BATCH_START, MI_BATCH_END
423be1da707SZhi Wang */
4244f870f1fSGao, Fred #define F_IP_ADVANCE_CUSTOM (1<<2)
425be1da707SZhi Wang u32 flag;
426be1da707SZhi Wang
4278a68d464SChris Wilson #define R_RCS BIT(RCS0)
4288a68d464SChris Wilson #define R_VCS1 BIT(VCS0)
4298a68d464SChris Wilson #define R_VCS2 BIT(VCS1)
430be1da707SZhi Wang #define R_VCS (R_VCS1 | R_VCS2)
4318a68d464SChris Wilson #define R_BCS BIT(BCS0)
4328a68d464SChris Wilson #define R_VECS BIT(VECS0)
433be1da707SZhi Wang #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
434be1da707SZhi Wang /* rings that support this cmd: BLT/RCS/VCS/VECS */
43593d9e045SMatt Roper intel_engine_mask_t rings;
436be1da707SZhi Wang
437be1da707SZhi Wang /* devices that support this cmd: SNB/IVB/HSW/... */
4382e679d48SJani Nikula u16 devices;
439be1da707SZhi Wang
440be1da707SZhi Wang /* which DWords are address that need fix up.
441be1da707SZhi Wang * bit 0 means a 32-bit non address operand in command
442be1da707SZhi Wang * bit 1 means address operand, which could be 32-bit
443be1da707SZhi Wang * or 64-bit depending on different architectures.(
444be1da707SZhi Wang * defined by "gmadr_bytes_in_cmd" in intel_gvt.
445be1da707SZhi Wang * No matter the address length, each address only takes
446be1da707SZhi Wang * one bit in the bitmap.
447be1da707SZhi Wang */
4482e679d48SJani Nikula u16 addr_bitmap;
449be1da707SZhi Wang
450be1da707SZhi Wang /* flag == F_LEN_CONST : command length
451be1da707SZhi Wang * flag == F_LEN_VAR : length bias bits
452be1da707SZhi Wang * Note: length is in DWord
453be1da707SZhi Wang */
4544f870f1fSGao, Fred u32 len;
455be1da707SZhi Wang
456be1da707SZhi Wang parser_cmd_handler handler;
4574f870f1fSGao, Fred
4584f870f1fSGao, Fred /* valid length in DWord */
4594f870f1fSGao, Fred u32 valid_len;
460be1da707SZhi Wang };
461be1da707SZhi Wang
462be1da707SZhi Wang struct cmd_entry {
463be1da707SZhi Wang struct hlist_node hlist;
464b007065aSJani Nikula const struct cmd_info *info;
465be1da707SZhi Wang };
466be1da707SZhi Wang
467be1da707SZhi Wang enum {
468be1da707SZhi Wang RING_BUFFER_INSTRUCTION,
469be1da707SZhi Wang BATCH_BUFFER_INSTRUCTION,
470be1da707SZhi Wang BATCH_BUFFER_2ND_LEVEL,
471493f30cdSYan Zhao RING_BUFFER_CTX,
472be1da707SZhi Wang };
473be1da707SZhi Wang
474be1da707SZhi Wang enum {
475be1da707SZhi Wang GTT_BUFFER,
476be1da707SZhi Wang PPGTT_BUFFER
477be1da707SZhi Wang };
478be1da707SZhi Wang
479be1da707SZhi Wang struct parser_exec_state {
480be1da707SZhi Wang struct intel_vgpu *vgpu;
4818fde4107SChris Wilson const struct intel_engine_cs *engine;
482be1da707SZhi Wang
483be1da707SZhi Wang int buf_type;
484be1da707SZhi Wang
485be1da707SZhi Wang /* batch buffer address type */
486be1da707SZhi Wang int buf_addr_type;
487be1da707SZhi Wang
488be1da707SZhi Wang /* graphics memory address of ring buffer start */
489be1da707SZhi Wang unsigned long ring_start;
490be1da707SZhi Wang unsigned long ring_size;
491be1da707SZhi Wang unsigned long ring_head;
492be1da707SZhi Wang unsigned long ring_tail;
493be1da707SZhi Wang
494be1da707SZhi Wang /* instruction graphics memory address */
495be1da707SZhi Wang unsigned long ip_gma;
496be1da707SZhi Wang
497be1da707SZhi Wang /* mapped va of the instr_gma */
498be1da707SZhi Wang void *ip_va;
499be1da707SZhi Wang void *rb_va;
500be1da707SZhi Wang
501be1da707SZhi Wang void *ret_bb_va;
502be1da707SZhi Wang /* next instruction when return from batch buffer to ring buffer */
503be1da707SZhi Wang unsigned long ret_ip_gma_ring;
504be1da707SZhi Wang
505be1da707SZhi Wang /* next instruction when return from 2nd batch buffer to batch buffer */
506be1da707SZhi Wang unsigned long ret_ip_gma_bb;
507be1da707SZhi Wang
508be1da707SZhi Wang /* batch buffer address type (GTT or PPGTT)
509be1da707SZhi Wang * used when ret from 2nd level batch buffer
510be1da707SZhi Wang */
511be1da707SZhi Wang int saved_buf_addr_type;
512ef75c685Sfred gao bool is_ctx_wa;
513493f30cdSYan Zhao bool is_init_ctx;
514be1da707SZhi Wang
515b007065aSJani Nikula const struct cmd_info *info;
516be1da707SZhi Wang
517be1da707SZhi Wang struct intel_vgpu_workload *workload;
518be1da707SZhi Wang };
519be1da707SZhi Wang
520be1da707SZhi Wang #define gmadr_dw_number(s) \
521be1da707SZhi Wang (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
522be1da707SZhi Wang
523999ccb40SDu, Changbin static unsigned long bypass_scan_mask = 0;
524be1da707SZhi Wang
525be1da707SZhi Wang /* ring ALL, type = 0 */
526ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mi[] = {
527be1da707SZhi Wang {31, 29},
528be1da707SZhi Wang {28, 23},
529be1da707SZhi Wang };
530be1da707SZhi Wang
531ed8cce30SJani Nikula static const struct decode_info decode_info_mi = {
532be1da707SZhi Wang "MI",
533be1da707SZhi Wang OP_LEN_MI,
534be1da707SZhi Wang ARRAY_SIZE(sub_op_mi),
535be1da707SZhi Wang sub_op_mi,
536be1da707SZhi Wang };
537be1da707SZhi Wang
538be1da707SZhi Wang /* ring RCS, command type 2 */
539ed8cce30SJani Nikula static const struct sub_op_bits sub_op_2d[] = {
540be1da707SZhi Wang {31, 29},
541be1da707SZhi Wang {28, 22},
542be1da707SZhi Wang };
543be1da707SZhi Wang
544ed8cce30SJani Nikula static const struct decode_info decode_info_2d = {
545be1da707SZhi Wang "2D",
546be1da707SZhi Wang OP_LEN_2D,
547be1da707SZhi Wang ARRAY_SIZE(sub_op_2d),
548be1da707SZhi Wang sub_op_2d,
549be1da707SZhi Wang };
550be1da707SZhi Wang
551be1da707SZhi Wang /* ring RCS, command type 3 */
552ed8cce30SJani Nikula static const struct sub_op_bits sub_op_3d_media[] = {
553be1da707SZhi Wang {31, 29},
554be1da707SZhi Wang {28, 27},
555be1da707SZhi Wang {26, 24},
556be1da707SZhi Wang {23, 16},
557be1da707SZhi Wang };
558be1da707SZhi Wang
559ed8cce30SJani Nikula static const struct decode_info decode_info_3d_media = {
560be1da707SZhi Wang "3D_Media",
561be1da707SZhi Wang OP_LEN_3D_MEDIA,
562be1da707SZhi Wang ARRAY_SIZE(sub_op_3d_media),
563be1da707SZhi Wang sub_op_3d_media,
564be1da707SZhi Wang };
565be1da707SZhi Wang
566be1da707SZhi Wang /* ring VCS, command type 3 */
567ed8cce30SJani Nikula static const struct sub_op_bits sub_op_mfx_vc[] = {
568be1da707SZhi Wang {31, 29},
569be1da707SZhi Wang {28, 27},
570be1da707SZhi Wang {26, 24},
571be1da707SZhi Wang {23, 21},
572be1da707SZhi Wang {20, 16},
573be1da707SZhi Wang };
574be1da707SZhi Wang
575ed8cce30SJani Nikula static const struct decode_info decode_info_mfx_vc = {
576be1da707SZhi Wang "MFX_VC",
577be1da707SZhi Wang OP_LEN_MFX_VC,
578be1da707SZhi Wang ARRAY_SIZE(sub_op_mfx_vc),
579be1da707SZhi Wang sub_op_mfx_vc,
580be1da707SZhi Wang };
581be1da707SZhi Wang
582be1da707SZhi Wang /* ring VECS, command type 3 */
583ed8cce30SJani Nikula static const struct sub_op_bits sub_op_vebox[] = {
584be1da707SZhi Wang {31, 29},
585be1da707SZhi Wang {28, 27},
586be1da707SZhi Wang {26, 24},
587be1da707SZhi Wang {23, 21},
588be1da707SZhi Wang {20, 16},
589be1da707SZhi Wang };
590be1da707SZhi Wang
591ed8cce30SJani Nikula static const struct decode_info decode_info_vebox = {
592be1da707SZhi Wang "VEBOX",
593be1da707SZhi Wang OP_LEN_VEBOX,
594be1da707SZhi Wang ARRAY_SIZE(sub_op_vebox),
595be1da707SZhi Wang sub_op_vebox,
596be1da707SZhi Wang };
597be1da707SZhi Wang
598ed8cce30SJani Nikula static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
5998a68d464SChris Wilson [RCS0] = {
600be1da707SZhi Wang &decode_info_mi,
601be1da707SZhi Wang NULL,
602be1da707SZhi Wang NULL,
603be1da707SZhi Wang &decode_info_3d_media,
604be1da707SZhi Wang NULL,
605be1da707SZhi Wang NULL,
606be1da707SZhi Wang NULL,
607be1da707SZhi Wang NULL,
608be1da707SZhi Wang },
609be1da707SZhi Wang
6108a68d464SChris Wilson [VCS0] = {
611be1da707SZhi Wang &decode_info_mi,
612be1da707SZhi Wang NULL,
613be1da707SZhi Wang NULL,
614be1da707SZhi Wang &decode_info_mfx_vc,
615be1da707SZhi Wang NULL,
616be1da707SZhi Wang NULL,
617be1da707SZhi Wang NULL,
618be1da707SZhi Wang NULL,
619be1da707SZhi Wang },
620be1da707SZhi Wang
6218a68d464SChris Wilson [BCS0] = {
622be1da707SZhi Wang &decode_info_mi,
623be1da707SZhi Wang NULL,
624be1da707SZhi Wang &decode_info_2d,
625be1da707SZhi Wang NULL,
626be1da707SZhi Wang NULL,
627be1da707SZhi Wang NULL,
628be1da707SZhi Wang NULL,
629be1da707SZhi Wang NULL,
630be1da707SZhi Wang },
631be1da707SZhi Wang
6328a68d464SChris Wilson [VECS0] = {
633be1da707SZhi Wang &decode_info_mi,
634be1da707SZhi Wang NULL,
635be1da707SZhi Wang NULL,
636be1da707SZhi Wang &decode_info_vebox,
637be1da707SZhi Wang NULL,
638be1da707SZhi Wang NULL,
639be1da707SZhi Wang NULL,
640be1da707SZhi Wang NULL,
641be1da707SZhi Wang },
642be1da707SZhi Wang
6438a68d464SChris Wilson [VCS1] = {
644be1da707SZhi Wang &decode_info_mi,
645be1da707SZhi Wang NULL,
646be1da707SZhi Wang NULL,
647be1da707SZhi Wang &decode_info_mfx_vc,
648be1da707SZhi Wang NULL,
649be1da707SZhi Wang NULL,
650be1da707SZhi Wang NULL,
651be1da707SZhi Wang NULL,
652be1da707SZhi Wang },
653be1da707SZhi Wang };
654be1da707SZhi Wang
get_opcode(u32 cmd,const struct intel_engine_cs * engine)6558fde4107SChris Wilson static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
656be1da707SZhi Wang {
657ed8cce30SJani Nikula const struct decode_info *d_info;
658be1da707SZhi Wang
6598fde4107SChris Wilson d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
660be1da707SZhi Wang if (d_info == NULL)
661be1da707SZhi Wang return INVALID_OP;
662be1da707SZhi Wang
663be1da707SZhi Wang return cmd >> (32 - d_info->op_len);
664be1da707SZhi Wang }
665be1da707SZhi Wang
6668fde4107SChris Wilson static inline const struct cmd_info *
find_cmd_entry(struct intel_gvt * gvt,unsigned int opcode,const struct intel_engine_cs * engine)6678fde4107SChris Wilson find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
6688fde4107SChris Wilson const struct intel_engine_cs *engine)
669be1da707SZhi Wang {
670be1da707SZhi Wang struct cmd_entry *e;
671be1da707SZhi Wang
672be1da707SZhi Wang hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
6738fde4107SChris Wilson if (opcode == e->info->opcode &&
6748fde4107SChris Wilson e->info->rings & engine->mask)
675be1da707SZhi Wang return e->info;
676be1da707SZhi Wang }
677be1da707SZhi Wang return NULL;
678be1da707SZhi Wang }
679be1da707SZhi Wang
6808fde4107SChris Wilson static inline const struct cmd_info *
get_cmd_info(struct intel_gvt * gvt,u32 cmd,const struct intel_engine_cs * engine)6818fde4107SChris Wilson get_cmd_info(struct intel_gvt *gvt, u32 cmd,
6828fde4107SChris Wilson const struct intel_engine_cs *engine)
683be1da707SZhi Wang {
684be1da707SZhi Wang u32 opcode;
685be1da707SZhi Wang
6868fde4107SChris Wilson opcode = get_opcode(cmd, engine);
687be1da707SZhi Wang if (opcode == INVALID_OP)
688be1da707SZhi Wang return NULL;
689be1da707SZhi Wang
6908fde4107SChris Wilson return find_cmd_entry(gvt, opcode, engine);
691be1da707SZhi Wang }
692be1da707SZhi Wang
sub_op_val(u32 cmd,u32 hi,u32 low)693be1da707SZhi Wang static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
694be1da707SZhi Wang {
695be1da707SZhi Wang return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
696be1da707SZhi Wang }
697be1da707SZhi Wang
print_opcode(u32 cmd,const struct intel_engine_cs * engine)6988fde4107SChris Wilson static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
699be1da707SZhi Wang {
700ed8cce30SJani Nikula const struct decode_info *d_info;
701be1da707SZhi Wang int i;
702be1da707SZhi Wang
7038fde4107SChris Wilson d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
704be1da707SZhi Wang if (d_info == NULL)
705be1da707SZhi Wang return;
706be1da707SZhi Wang
707627c845cSTina Zhang gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
708be1da707SZhi Wang cmd >> (32 - d_info->op_len), d_info->name);
709be1da707SZhi Wang
710be1da707SZhi Wang for (i = 0; i < d_info->nr_sub_op; i++)
711be1da707SZhi Wang pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
712be1da707SZhi Wang d_info->sub_op[i].low));
713be1da707SZhi Wang
714be1da707SZhi Wang pr_err("\n");
715be1da707SZhi Wang }
716be1da707SZhi Wang
cmd_ptr(struct parser_exec_state * s,int index)717be1da707SZhi Wang static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
718be1da707SZhi Wang {
719be1da707SZhi Wang return s->ip_va + (index << 2);
720be1da707SZhi Wang }
721be1da707SZhi Wang
cmd_val(struct parser_exec_state * s,int index)722be1da707SZhi Wang static inline u32 cmd_val(struct parser_exec_state *s, int index)
723be1da707SZhi Wang {
724be1da707SZhi Wang return *cmd_ptr(s, index);
725be1da707SZhi Wang }
726be1da707SZhi Wang
is_init_ctx(struct parser_exec_state * s)727493f30cdSYan Zhao static inline bool is_init_ctx(struct parser_exec_state *s)
728493f30cdSYan Zhao {
729493f30cdSYan Zhao return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
730493f30cdSYan Zhao }
731493f30cdSYan Zhao
parser_exec_state_dump(struct parser_exec_state * s)732be1da707SZhi Wang static void parser_exec_state_dump(struct parser_exec_state *s)
733be1da707SZhi Wang {
734be1da707SZhi Wang int cnt = 0;
735be1da707SZhi Wang int i;
736be1da707SZhi Wang
7378fde4107SChris Wilson gvt_dbg_cmd(" vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
7388fde4107SChris Wilson " ring_head(%08lx) ring_tail(%08lx)\n",
7398fde4107SChris Wilson s->vgpu->id, s->engine->name,
7408fde4107SChris Wilson s->ring_start, s->ring_start + s->ring_size,
741be1da707SZhi Wang s->ring_head, s->ring_tail);
742be1da707SZhi Wang
743627c845cSTina Zhang gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
744be1da707SZhi Wang s->buf_type == RING_BUFFER_INSTRUCTION ?
745493f30cdSYan Zhao "RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
746493f30cdSYan Zhao "CTX_BUFFER" : "BATCH_BUFFER"),
747be1da707SZhi Wang s->buf_addr_type == GTT_BUFFER ?
748be1da707SZhi Wang "GTT" : "PPGTT", s->ip_gma);
749be1da707SZhi Wang
750be1da707SZhi Wang if (s->ip_va == NULL) {
751627c845cSTina Zhang gvt_dbg_cmd(" ip_va(NULL)");
752be1da707SZhi Wang return;
753be1da707SZhi Wang }
754be1da707SZhi Wang
755627c845cSTina Zhang gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
756be1da707SZhi Wang s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
757be1da707SZhi Wang cmd_val(s, 2), cmd_val(s, 3));
758be1da707SZhi Wang
7598fde4107SChris Wilson print_opcode(cmd_val(s, 0), s->engine);
760be1da707SZhi Wang
761be1da707SZhi Wang s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
762be1da707SZhi Wang
763be1da707SZhi Wang while (cnt < 1024) {
764e4aeba69SChangbin Du gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
765be1da707SZhi Wang for (i = 0; i < 8; i++)
766e4aeba69SChangbin Du gvt_dbg_cmd("%08x ", cmd_val(s, i));
767e4aeba69SChangbin Du gvt_dbg_cmd("\n");
768be1da707SZhi Wang
769be1da707SZhi Wang s->ip_va += 8 * sizeof(u32);
770be1da707SZhi Wang cnt += 8;
771be1da707SZhi Wang }
772be1da707SZhi Wang }
773be1da707SZhi Wang
update_ip_va(struct parser_exec_state * s)774be1da707SZhi Wang static inline void update_ip_va(struct parser_exec_state *s)
775be1da707SZhi Wang {
776be1da707SZhi Wang unsigned long len = 0;
777be1da707SZhi Wang
778be1da707SZhi Wang if (WARN_ON(s->ring_head == s->ring_tail))
779be1da707SZhi Wang return;
780be1da707SZhi Wang
781493f30cdSYan Zhao if (s->buf_type == RING_BUFFER_INSTRUCTION ||
782493f30cdSYan Zhao s->buf_type == RING_BUFFER_CTX) {
783be1da707SZhi Wang unsigned long ring_top = s->ring_start + s->ring_size;
784be1da707SZhi Wang
785be1da707SZhi Wang if (s->ring_head > s->ring_tail) {
786be1da707SZhi Wang if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
787be1da707SZhi Wang len = (s->ip_gma - s->ring_head);
788be1da707SZhi Wang else if (s->ip_gma >= s->ring_start &&
789be1da707SZhi Wang s->ip_gma <= s->ring_tail)
790be1da707SZhi Wang len = (ring_top - s->ring_head) +
791be1da707SZhi Wang (s->ip_gma - s->ring_start);
792be1da707SZhi Wang } else
793be1da707SZhi Wang len = (s->ip_gma - s->ring_head);
794be1da707SZhi Wang
795be1da707SZhi Wang s->ip_va = s->rb_va + len;
796be1da707SZhi Wang } else {/* shadow batch buffer */
797be1da707SZhi Wang s->ip_va = s->ret_bb_va;
798be1da707SZhi Wang }
799be1da707SZhi Wang }
800be1da707SZhi Wang
ip_gma_set(struct parser_exec_state * s,unsigned long ip_gma)801be1da707SZhi Wang static inline int ip_gma_set(struct parser_exec_state *s,
802be1da707SZhi Wang unsigned long ip_gma)
803be1da707SZhi Wang {
804be1da707SZhi Wang WARN_ON(!IS_ALIGNED(ip_gma, 4));
805be1da707SZhi Wang
806be1da707SZhi Wang s->ip_gma = ip_gma;
807be1da707SZhi Wang update_ip_va(s);
808be1da707SZhi Wang return 0;
809be1da707SZhi Wang }
810be1da707SZhi Wang
ip_gma_advance(struct parser_exec_state * s,unsigned int dw_len)811be1da707SZhi Wang static inline int ip_gma_advance(struct parser_exec_state *s,
812be1da707SZhi Wang unsigned int dw_len)
813be1da707SZhi Wang {
814be1da707SZhi Wang s->ip_gma += (dw_len << 2);
815be1da707SZhi Wang
816be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) {
817be1da707SZhi Wang if (s->ip_gma >= s->ring_start + s->ring_size)
818be1da707SZhi Wang s->ip_gma -= s->ring_size;
819be1da707SZhi Wang update_ip_va(s);
820be1da707SZhi Wang } else {
821be1da707SZhi Wang s->ip_va += (dw_len << 2);
822be1da707SZhi Wang }
823be1da707SZhi Wang
824be1da707SZhi Wang return 0;
825be1da707SZhi Wang }
826be1da707SZhi Wang
get_cmd_length(const struct cmd_info * info,u32 cmd)827b007065aSJani Nikula static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
828be1da707SZhi Wang {
829be1da707SZhi Wang if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
830be1da707SZhi Wang return info->len;
831be1da707SZhi Wang else
832be1da707SZhi Wang return (cmd & ((1U << info->len) - 1)) + 2;
833be1da707SZhi Wang return 0;
834be1da707SZhi Wang }
835be1da707SZhi Wang
cmd_length(struct parser_exec_state * s)836be1da707SZhi Wang static inline int cmd_length(struct parser_exec_state *s)
837be1da707SZhi Wang {
838be1da707SZhi Wang return get_cmd_length(s->info, cmd_val(s, 0));
839be1da707SZhi Wang }
840be1da707SZhi Wang
841be1da707SZhi Wang /* do not remove this, some platform may need clflush here */
842be1da707SZhi Wang #define patch_value(s, addr, val) do { \
843be1da707SZhi Wang *addr = val; \
844be1da707SZhi Wang } while (0)
845be1da707SZhi Wang
is_mocs_mmio(unsigned int offset)846f402f2d6SWeinan Li static inline bool is_mocs_mmio(unsigned int offset)
847f402f2d6SWeinan Li {
848f402f2d6SWeinan Li return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
849f402f2d6SWeinan Li ((offset >= 0xb020) && (offset <= 0xb0a0));
850f402f2d6SWeinan Li }
851f402f2d6SWeinan Li
is_cmd_update_pdps(unsigned int offset,struct parser_exec_state * s)852bec3df93SZhenyu Wang static int is_cmd_update_pdps(unsigned int offset,
853bec3df93SZhenyu Wang struct parser_exec_state *s)
854bec3df93SZhenyu Wang {
855bec3df93SZhenyu Wang u32 base = s->workload->engine->mmio_base;
856bec3df93SZhenyu Wang return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
857bec3df93SZhenyu Wang }
858bec3df93SZhenyu Wang
cmd_pdp_mmio_update_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index)859bec3df93SZhenyu Wang static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
860bec3df93SZhenyu Wang unsigned int offset, unsigned int index)
861bec3df93SZhenyu Wang {
862bec3df93SZhenyu Wang struct intel_vgpu *vgpu = s->vgpu;
863bec3df93SZhenyu Wang struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
864bec3df93SZhenyu Wang struct intel_vgpu_mm *mm;
865bec3df93SZhenyu Wang u64 pdps[GEN8_3LVL_PDPES];
866bec3df93SZhenyu Wang
867bec3df93SZhenyu Wang if (shadow_mm->ppgtt_mm.root_entry_type ==
868bec3df93SZhenyu Wang GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
869bec3df93SZhenyu Wang pdps[0] = (u64)cmd_val(s, 2) << 32;
870bec3df93SZhenyu Wang pdps[0] |= cmd_val(s, 4);
871bec3df93SZhenyu Wang
872bec3df93SZhenyu Wang mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
873bec3df93SZhenyu Wang if (!mm) {
874bec3df93SZhenyu Wang gvt_vgpu_err("failed to get the 4-level shadow vm\n");
875bec3df93SZhenyu Wang return -EINVAL;
876bec3df93SZhenyu Wang }
877bec3df93SZhenyu Wang intel_vgpu_mm_get(mm);
878bec3df93SZhenyu Wang list_add_tail(&mm->ppgtt_mm.link,
879bec3df93SZhenyu Wang &s->workload->lri_shadow_mm);
880bec3df93SZhenyu Wang *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
881bec3df93SZhenyu Wang *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
882bec3df93SZhenyu Wang } else {
883bec3df93SZhenyu Wang /* Currently all guests use PML4 table and now can't
884bec3df93SZhenyu Wang * have a guest with 3-level table but uses LRI for
885bec3df93SZhenyu Wang * PPGTT update. So this is simply un-testable. */
886bec3df93SZhenyu Wang GEM_BUG_ON(1);
887bec3df93SZhenyu Wang gvt_vgpu_err("invalid shared shadow vm type\n");
888bec3df93SZhenyu Wang return -EINVAL;
889bec3df93SZhenyu Wang }
890bec3df93SZhenyu Wang return 0;
891bec3df93SZhenyu Wang }
892bec3df93SZhenyu Wang
cmd_reg_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index,char * cmd)893be1da707SZhi Wang static int cmd_reg_handler(struct parser_exec_state *s,
894be1da707SZhi Wang unsigned int offset, unsigned int index, char *cmd)
895be1da707SZhi Wang {
896be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu;
897be1da707SZhi Wang struct intel_gvt *gvt = vgpu->gvt;
8986cef21a1SHang Yuan u32 ctx_sr_ctl;
89902dd2b12SYan Zhao u32 *vreg, vreg_old;
900be1da707SZhi Wang
901be1da707SZhi Wang if (offset + 4 > gvt->device_info.mmio_size) {
902695fbc08STina Zhang gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
903be1da707SZhi Wang cmd, offset);
9045c56883aSfred gao return -EFAULT;
905be1da707SZhi Wang }
906be1da707SZhi Wang
907493f30cdSYan Zhao if (is_init_ctx(s)) {
908b7ccb10eSYan Zhao struct intel_gvt_mmio_info *mmio_info;
909b7ccb10eSYan Zhao
910493f30cdSYan Zhao intel_gvt_mmio_set_cmd_accessible(gvt, offset);
911b7ccb10eSYan Zhao mmio_info = intel_gvt_find_mmio_info(gvt, offset);
912b7ccb10eSYan Zhao if (mmio_info && mmio_info->write)
913b7ccb10eSYan Zhao intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
914493f30cdSYan Zhao return 0;
915493f30cdSYan Zhao }
916493f30cdSYan Zhao
9177e93a080SYan Zhao if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
918695fbc08STina Zhang gvt_vgpu_err("%s access to non-render register (%x)\n",
919695fbc08STina Zhang cmd, offset);
9208d458ea0SZhao Yan return -EBADRQC;
921be1da707SZhi Wang }
922be1da707SZhi Wang
923f18d417aSYan Zhao if (!strncmp(cmd, "srm", 3) ||
924f18d417aSYan Zhao !strncmp(cmd, "lrm", 3)) {
9256b5b2a5bSZhenyu Wang if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
9266b5b2a5bSZhenyu Wang offset == 0x21f0 ||
9276b5b2a5bSZhenyu Wang (IS_BROADWELL(gvt->gt->i915) &&
9286b5b2a5bSZhenyu Wang offset == i915_mmio_reg_offset(INSTPM)))
9296b5b2a5bSZhenyu Wang return 0;
9306b5b2a5bSZhenyu Wang else {
931f18d417aSYan Zhao gvt_vgpu_err("%s access to register (%x)\n",
932f18d417aSYan Zhao cmd, offset);
933f18d417aSYan Zhao return -EPERM;
9346b5b2a5bSZhenyu Wang }
935f18d417aSYan Zhao }
936f18d417aSYan Zhao
93773a37a43SYan Zhao if (!strncmp(cmd, "lrr-src", 7) ||
93873a37a43SYan Zhao !strncmp(cmd, "lrr-dst", 7)) {
9396b5b2a5bSZhenyu Wang if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
9406b5b2a5bSZhenyu Wang return 0;
9416b5b2a5bSZhenyu Wang else {
9426b5b2a5bSZhenyu Wang gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
94373a37a43SYan Zhao return -EPERM;
94473a37a43SYan Zhao }
9456b5b2a5bSZhenyu Wang }
94673a37a43SYan Zhao
947252cec9fSYan Zhao if (!strncmp(cmd, "pipe_ctrl", 9)) {
948252cec9fSYan Zhao /* TODO: add LRI POST logic here */
949252cec9fSYan Zhao return 0;
950252cec9fSYan Zhao }
951252cec9fSYan Zhao
95202dd2b12SYan Zhao if (strncmp(cmd, "lri", 3))
95302dd2b12SYan Zhao return -EPERM;
95402dd2b12SYan Zhao
95502dd2b12SYan Zhao /* below are all lri handlers */
95602dd2b12SYan Zhao vreg = &vgpu_vreg(s->vgpu, offset);
95702dd2b12SYan Zhao
958bec3df93SZhenyu Wang if (is_cmd_update_pdps(offset, s) &&
959bec3df93SZhenyu Wang cmd_pdp_mmio_update_handler(s, offset, index))
960bec3df93SZhenyu Wang return -EINVAL;
961bec3df93SZhenyu Wang
96202dd2b12SYan Zhao if (offset == i915_mmio_reg_offset(DERRMR) ||
96302dd2b12SYan Zhao offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
96402dd2b12SYan Zhao /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
96502dd2b12SYan Zhao patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
96602dd2b12SYan Zhao }
96702dd2b12SYan Zhao
96802dd2b12SYan Zhao if (is_mocs_mmio(offset))
96902dd2b12SYan Zhao *vreg = cmd_val(s, index + 1);
97002dd2b12SYan Zhao
97102dd2b12SYan Zhao vreg_old = *vreg;
97202dd2b12SYan Zhao
97302dd2b12SYan Zhao if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
97402dd2b12SYan Zhao u32 cmdval_new, cmdval;
97502dd2b12SYan Zhao struct intel_gvt_mmio_info *mmio_info;
97602dd2b12SYan Zhao
97702dd2b12SYan Zhao cmdval = cmd_val(s, index + 1);
97802dd2b12SYan Zhao
97902dd2b12SYan Zhao mmio_info = intel_gvt_find_mmio_info(gvt, offset);
98002dd2b12SYan Zhao if (!mmio_info) {
98102dd2b12SYan Zhao cmdval_new = cmdval;
98202dd2b12SYan Zhao } else {
98302dd2b12SYan Zhao u64 ro_mask = mmio_info->ro_mask;
98402dd2b12SYan Zhao int ret;
98502dd2b12SYan Zhao
98602dd2b12SYan Zhao if (likely(!ro_mask))
98702dd2b12SYan Zhao ret = mmio_info->write(s->vgpu, offset,
98802dd2b12SYan Zhao &cmdval, 4);
98902dd2b12SYan Zhao else {
99002dd2b12SYan Zhao gvt_vgpu_err("try to write RO reg %x\n",
99102dd2b12SYan Zhao offset);
99202dd2b12SYan Zhao ret = -EBADRQC;
99302dd2b12SYan Zhao }
99402dd2b12SYan Zhao if (ret)
99502dd2b12SYan Zhao return ret;
99602dd2b12SYan Zhao cmdval_new = *vreg;
99702dd2b12SYan Zhao }
99802dd2b12SYan Zhao if (cmdval_new != cmdval)
99902dd2b12SYan Zhao patch_value(s, cmd_ptr(s, index+1), cmdval_new);
100002dd2b12SYan Zhao }
100102dd2b12SYan Zhao
100202dd2b12SYan Zhao /* only patch cmd. restore vreg value if changed in mmio write handler*/
100302dd2b12SYan Zhao *vreg = vreg_old;
100402dd2b12SYan Zhao
10056cef21a1SHang Yuan /* TODO
1006df2ea3c2SYan Zhao * In order to let workload with inhibit context to generate
1007df2ea3c2SYan Zhao * correct image data into memory, vregs values will be loaded to
1008df2ea3c2SYan Zhao * hw via LRIs in the workload with inhibit context. But as
1009df2ea3c2SYan Zhao * indirect context is loaded prior to LRIs in workload, we don't
1010df2ea3c2SYan Zhao * want reg values specified in indirect context overwritten by
1011df2ea3c2SYan Zhao * LRIs in workloads. So, when scanning an indirect context, we
1012df2ea3c2SYan Zhao * update reg values in it into vregs, so LRIs in workload with
1013df2ea3c2SYan Zhao * inhibit context will restore with correct values
10146cef21a1SHang Yuan */
1015d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) == 9 &&
101656d44649SYan Zhao intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
10176cef21a1SHang Yuan !strncmp(cmd, "lri", 3)) {
1018e3d7640eSChristoph Hellwig intel_gvt_read_gpa(s->vgpu,
10196cef21a1SHang Yuan s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
10206cef21a1SHang Yuan /* check inhibit context */
10216cef21a1SHang Yuan if (ctx_sr_ctl & 1) {
10226cef21a1SHang Yuan u32 data = cmd_val(s, index + 1);
10236cef21a1SHang Yuan
10246cef21a1SHang Yuan if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
10256cef21a1SHang Yuan intel_vgpu_mask_mmio_write(vgpu,
10266cef21a1SHang Yuan offset, &data, 4);
10276cef21a1SHang Yuan else
10286cef21a1SHang Yuan vgpu_vreg(vgpu, offset) = data;
10296cef21a1SHang Yuan }
10306cef21a1SHang Yuan }
10316cef21a1SHang Yuan
1032be1da707SZhi Wang return 0;
1033be1da707SZhi Wang }
1034be1da707SZhi Wang
1035be1da707SZhi Wang #define cmd_reg(s, i) \
1036be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 2))
1037be1da707SZhi Wang
1038be1da707SZhi Wang #define cmd_reg_inhibit(s, i) \
1039be1da707SZhi Wang (cmd_val(s, i) & GENMASK(22, 18))
1040be1da707SZhi Wang
1041be1da707SZhi Wang #define cmd_gma(s, i) \
1042be1da707SZhi Wang (cmd_val(s, i) & GENMASK(31, 2))
1043be1da707SZhi Wang
1044be1da707SZhi Wang #define cmd_gma_hi(s, i) \
1045be1da707SZhi Wang (cmd_val(s, i) & GENMASK(15, 0))
1046be1da707SZhi Wang
cmd_handler_lri(struct parser_exec_state * s)1047be1da707SZhi Wang static int cmd_handler_lri(struct parser_exec_state *s)
1048be1da707SZhi Wang {
1049be1da707SZhi Wang int i, ret = 0;
1050be1da707SZhi Wang int cmd_len = cmd_length(s);
1051be1da707SZhi Wang
1052be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) {
10538fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
10548fde4107SChris Wilson if (s->engine->id == BCS0 &&
10558a68d464SChris Wilson cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1056be1da707SZhi Wang ret |= 0;
1057be1da707SZhi Wang else
10588a68d464SChris Wilson ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1059be1da707SZhi Wang }
1060be1da707SZhi Wang if (ret)
1061be1da707SZhi Wang break;
1062be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
10635c56883aSfred gao if (ret)
10645c56883aSfred gao break;
1065be1da707SZhi Wang }
1066be1da707SZhi Wang return ret;
1067be1da707SZhi Wang }
1068be1da707SZhi Wang
cmd_handler_lrr(struct parser_exec_state * s)1069be1da707SZhi Wang static int cmd_handler_lrr(struct parser_exec_state *s)
1070be1da707SZhi Wang {
1071be1da707SZhi Wang int i, ret = 0;
1072be1da707SZhi Wang int cmd_len = cmd_length(s);
1073be1da707SZhi Wang
1074be1da707SZhi Wang for (i = 1; i < cmd_len; i += 2) {
10758fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915))
1076be1da707SZhi Wang ret |= ((cmd_reg_inhibit(s, i) ||
1077be1da707SZhi Wang (cmd_reg_inhibit(s, i + 1)))) ?
10785c56883aSfred gao -EBADRQC : 0;
1079be1da707SZhi Wang if (ret)
1080be1da707SZhi Wang break;
1081be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
10825c56883aSfred gao if (ret)
10835c56883aSfred gao break;
1084be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
10855c56883aSfred gao if (ret)
10865c56883aSfred gao break;
1087be1da707SZhi Wang }
1088be1da707SZhi Wang return ret;
1089be1da707SZhi Wang }
1090be1da707SZhi Wang
1091be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s,
1092be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode);
1093be1da707SZhi Wang
cmd_handler_lrm(struct parser_exec_state * s)1094be1da707SZhi Wang static int cmd_handler_lrm(struct parser_exec_state *s)
1095be1da707SZhi Wang {
1096be1da707SZhi Wang struct intel_gvt *gvt = s->vgpu->gvt;
1097be1da707SZhi Wang int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1098be1da707SZhi Wang unsigned long gma;
1099be1da707SZhi Wang int i, ret = 0;
1100be1da707SZhi Wang int cmd_len = cmd_length(s);
1101be1da707SZhi Wang
1102be1da707SZhi Wang for (i = 1; i < cmd_len;) {
11038fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915))
11045c56883aSfred gao ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1105be1da707SZhi Wang if (ret)
1106be1da707SZhi Wang break;
1107be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
11085c56883aSfred gao if (ret)
11095c56883aSfred gao break;
1110be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) {
1111be1da707SZhi Wang gma = cmd_gma(s, i + 1);
1112be1da707SZhi Wang if (gmadr_bytes == 8)
1113be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32;
1114be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false);
11155c56883aSfred gao if (ret)
11165c56883aSfred gao break;
1117be1da707SZhi Wang }
1118be1da707SZhi Wang i += gmadr_dw_number(s) + 1;
1119be1da707SZhi Wang }
1120be1da707SZhi Wang return ret;
1121be1da707SZhi Wang }
1122be1da707SZhi Wang
cmd_handler_srm(struct parser_exec_state * s)1123be1da707SZhi Wang static int cmd_handler_srm(struct parser_exec_state *s)
1124be1da707SZhi Wang {
1125be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1126be1da707SZhi Wang unsigned long gma;
1127be1da707SZhi Wang int i, ret = 0;
1128be1da707SZhi Wang int cmd_len = cmd_length(s);
1129be1da707SZhi Wang
1130be1da707SZhi Wang for (i = 1; i < cmd_len;) {
1131be1da707SZhi Wang ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
11325c56883aSfred gao if (ret)
11335c56883aSfred gao break;
1134be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 22)) {
1135be1da707SZhi Wang gma = cmd_gma(s, i + 1);
1136be1da707SZhi Wang if (gmadr_bytes == 8)
1137be1da707SZhi Wang gma |= (cmd_gma_hi(s, i + 2)) << 32;
1138be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u32), false);
11395c56883aSfred gao if (ret)
11405c56883aSfred gao break;
1141be1da707SZhi Wang }
1142be1da707SZhi Wang i += gmadr_dw_number(s) + 1;
1143be1da707SZhi Wang }
1144be1da707SZhi Wang return ret;
1145be1da707SZhi Wang }
1146be1da707SZhi Wang
1147be1da707SZhi Wang struct cmd_interrupt_event {
1148be1da707SZhi Wang int pipe_control_notify;
1149be1da707SZhi Wang int mi_flush_dw;
1150be1da707SZhi Wang int mi_user_interrupt;
1151be1da707SZhi Wang };
1152be1da707SZhi Wang
11530b782e66SRikard Falkeborn static const struct cmd_interrupt_event cmd_interrupt_events[] = {
11548a68d464SChris Wilson [RCS0] = {
1155be1da707SZhi Wang .pipe_control_notify = RCS_PIPE_CONTROL,
1156be1da707SZhi Wang .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1157be1da707SZhi Wang .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1158be1da707SZhi Wang },
11598a68d464SChris Wilson [BCS0] = {
1160be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1161be1da707SZhi Wang .mi_flush_dw = BCS_MI_FLUSH_DW,
1162be1da707SZhi Wang .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1163be1da707SZhi Wang },
11648a68d464SChris Wilson [VCS0] = {
1165be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1166be1da707SZhi Wang .mi_flush_dw = VCS_MI_FLUSH_DW,
1167be1da707SZhi Wang .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1168be1da707SZhi Wang },
11698a68d464SChris Wilson [VCS1] = {
1170be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1171be1da707SZhi Wang .mi_flush_dw = VCS2_MI_FLUSH_DW,
1172be1da707SZhi Wang .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1173be1da707SZhi Wang },
11748a68d464SChris Wilson [VECS0] = {
1175be1da707SZhi Wang .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1176be1da707SZhi Wang .mi_flush_dw = VECS_MI_FLUSH_DW,
1177be1da707SZhi Wang .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1178be1da707SZhi Wang },
1179be1da707SZhi Wang };
1180be1da707SZhi Wang
cmd_handler_pipe_control(struct parser_exec_state * s)1181be1da707SZhi Wang static int cmd_handler_pipe_control(struct parser_exec_state *s)
1182be1da707SZhi Wang {
1183be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1184be1da707SZhi Wang unsigned long gma;
1185be1da707SZhi Wang bool index_mode = false;
1186be1da707SZhi Wang unsigned int post_sync;
1187be1da707SZhi Wang int ret = 0;
1188ac071578SXiaolin Zhang u32 hws_pga, val;
1189be1da707SZhi Wang
1190be1da707SZhi Wang post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1191be1da707SZhi Wang
1192be1da707SZhi Wang /* LRI post sync */
1193be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1194be1da707SZhi Wang ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1195be1da707SZhi Wang /* post sync */
1196be1da707SZhi Wang else if (post_sync) {
1197be1da707SZhi Wang if (post_sync == 2)
1198be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1199be1da707SZhi Wang else if (post_sync == 3)
1200be1da707SZhi Wang ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1201be1da707SZhi Wang else if (post_sync == 1) {
1202be1da707SZhi Wang /* check ggtt*/
12033f765a34SYulei Zhang if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1204be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 3);
1205be1da707SZhi Wang if (gmadr_bytes == 8)
1206be1da707SZhi Wang gma |= (cmd_gma_hi(s, 3)) << 32;
1207be1da707SZhi Wang /* Store Data Index */
1208be1da707SZhi Wang if (cmd_val(s, 1) & (1 << 21))
1209be1da707SZhi Wang index_mode = true;
1210be1da707SZhi Wang ret |= cmd_address_audit(s, gma, sizeof(u64),
1211be1da707SZhi Wang index_mode);
1212ac071578SXiaolin Zhang if (ret)
1213ac071578SXiaolin Zhang return ret;
1214ac071578SXiaolin Zhang if (index_mode) {
12158fde4107SChris Wilson hws_pga = s->vgpu->hws_pga[s->engine->id];
1216ac071578SXiaolin Zhang gma = hws_pga + gma;
1217ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 2), gma);
1218ac071578SXiaolin Zhang val = cmd_val(s, 1) & (~(1 << 21));
1219ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), val);
1220ac071578SXiaolin Zhang }
1221be1da707SZhi Wang }
1222be1da707SZhi Wang }
1223be1da707SZhi Wang }
1224be1da707SZhi Wang
1225be1da707SZhi Wang if (ret)
1226be1da707SZhi Wang return ret;
1227be1da707SZhi Wang
1228be1da707SZhi Wang if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
12298fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1230be1da707SZhi Wang s->workload->pending_events);
1231be1da707SZhi Wang return 0;
1232be1da707SZhi Wang }
1233be1da707SZhi Wang
cmd_handler_mi_user_interrupt(struct parser_exec_state * s)1234be1da707SZhi Wang static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1235be1da707SZhi Wang {
12368fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1237be1da707SZhi Wang s->workload->pending_events);
12385da795b0SZhipeng Gong patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1239be1da707SZhi Wang return 0;
1240be1da707SZhi Wang }
1241be1da707SZhi Wang
cmd_advance_default(struct parser_exec_state * s)1242be1da707SZhi Wang static int cmd_advance_default(struct parser_exec_state *s)
1243be1da707SZhi Wang {
1244be1da707SZhi Wang return ip_gma_advance(s, cmd_length(s));
1245be1da707SZhi Wang }
1246be1da707SZhi Wang
cmd_handler_mi_batch_buffer_end(struct parser_exec_state * s)1247be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1248be1da707SZhi Wang {
1249be1da707SZhi Wang int ret;
1250be1da707SZhi Wang
1251be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1252be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION;
1253be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_bb);
1254be1da707SZhi Wang s->buf_addr_type = s->saved_buf_addr_type;
1255493f30cdSYan Zhao } else if (s->buf_type == RING_BUFFER_CTX) {
1256493f30cdSYan Zhao ret = ip_gma_set(s, s->ring_tail);
1257be1da707SZhi Wang } else {
1258be1da707SZhi Wang s->buf_type = RING_BUFFER_INSTRUCTION;
1259be1da707SZhi Wang s->buf_addr_type = GTT_BUFFER;
1260be1da707SZhi Wang if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1261be1da707SZhi Wang s->ret_ip_gma_ring -= s->ring_size;
1262be1da707SZhi Wang ret = ip_gma_set(s, s->ret_ip_gma_ring);
1263be1da707SZhi Wang }
1264be1da707SZhi Wang return ret;
1265be1da707SZhi Wang }
1266be1da707SZhi Wang
1267be1da707SZhi Wang struct mi_display_flip_command_info {
1268be1da707SZhi Wang int pipe;
1269be1da707SZhi Wang int plane;
1270be1da707SZhi Wang int event;
1271be1da707SZhi Wang i915_reg_t stride_reg;
1272be1da707SZhi Wang i915_reg_t ctrl_reg;
1273be1da707SZhi Wang i915_reg_t surf_reg;
1274be1da707SZhi Wang u64 stride_val;
1275be1da707SZhi Wang u64 tile_val;
1276be1da707SZhi Wang u64 surf_val;
1277be1da707SZhi Wang bool async_flip;
1278be1da707SZhi Wang };
1279be1da707SZhi Wang
1280be1da707SZhi Wang struct plane_code_mapping {
1281be1da707SZhi Wang int pipe;
1282be1da707SZhi Wang int plane;
1283be1da707SZhi Wang int event;
1284be1da707SZhi Wang };
1285be1da707SZhi Wang
gen8_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1286be1da707SZhi Wang static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1287be1da707SZhi Wang struct mi_display_flip_command_info *info)
1288be1da707SZhi Wang {
12898fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915;
1290be1da707SZhi Wang struct plane_code_mapping gen8_plane_code[] = {
1291be1da707SZhi Wang [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1292be1da707SZhi Wang [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1293be1da707SZhi Wang [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1294be1da707SZhi Wang [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1295be1da707SZhi Wang [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1296be1da707SZhi Wang [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1297be1da707SZhi Wang };
1298be1da707SZhi Wang u32 dword0, dword1, dword2;
1299be1da707SZhi Wang u32 v;
1300be1da707SZhi Wang
1301be1da707SZhi Wang dword0 = cmd_val(s, 0);
1302be1da707SZhi Wang dword1 = cmd_val(s, 1);
1303be1da707SZhi Wang dword2 = cmd_val(s, 2);
1304be1da707SZhi Wang
1305be1da707SZhi Wang v = (dword0 & GENMASK(21, 19)) >> 19;
1306db19c724SPankaj Bharadiya if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
13075c56883aSfred gao return -EBADRQC;
1308be1da707SZhi Wang
1309be1da707SZhi Wang info->pipe = gen8_plane_code[v].pipe;
1310be1da707SZhi Wang info->plane = gen8_plane_code[v].plane;
1311be1da707SZhi Wang info->event = gen8_plane_code[v].event;
1312be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1313be1da707SZhi Wang info->tile_val = (dword1 & 0x1);
1314be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1315be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1316be1da707SZhi Wang
1317be1da707SZhi Wang if (info->plane == PLANE_A) {
1318be30c827SJani Nikula info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1319cd962cdbSJani Nikula info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
13209e93147fSJani Nikula info->surf_reg = DSPSURF(dev_priv, info->pipe);
1321be1da707SZhi Wang } else if (info->plane == PLANE_B) {
1322be1da707SZhi Wang info->ctrl_reg = SPRCTL(info->pipe);
1323be1da707SZhi Wang info->stride_reg = SPRSTRIDE(info->pipe);
1324be1da707SZhi Wang info->surf_reg = SPRSURF(info->pipe);
1325be1da707SZhi Wang } else {
1326db19c724SPankaj Bharadiya drm_WARN_ON(&dev_priv->drm, 1);
13275c56883aSfred gao return -EBADRQC;
1328be1da707SZhi Wang }
1329be1da707SZhi Wang return 0;
1330be1da707SZhi Wang }
1331be1da707SZhi Wang
skl_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1332be1da707SZhi Wang static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1333be1da707SZhi Wang struct mi_display_flip_command_info *info)
1334be1da707SZhi Wang {
13358fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915;
1336695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1337be1da707SZhi Wang u32 dword0 = cmd_val(s, 0);
1338be1da707SZhi Wang u32 dword1 = cmd_val(s, 1);
1339be1da707SZhi Wang u32 dword2 = cmd_val(s, 2);
1340be1da707SZhi Wang u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1341be1da707SZhi Wang
13426e27d514SXu Han info->plane = PRIMARY_PLANE;
13436e27d514SXu Han
1344be1da707SZhi Wang switch (plane) {
1345be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1346be1da707SZhi Wang info->pipe = PIPE_A;
1347be1da707SZhi Wang info->event = PRIMARY_A_FLIP_DONE;
1348be1da707SZhi Wang break;
1349be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1350be1da707SZhi Wang info->pipe = PIPE_B;
1351be1da707SZhi Wang info->event = PRIMARY_B_FLIP_DONE;
1352be1da707SZhi Wang break;
1353be1da707SZhi Wang case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
135464fafcf5SMin He info->pipe = PIPE_C;
1355be1da707SZhi Wang info->event = PRIMARY_C_FLIP_DONE;
1356be1da707SZhi Wang break;
13576e27d514SXu Han
13586e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
13596e27d514SXu Han info->pipe = PIPE_A;
13606e27d514SXu Han info->event = SPRITE_A_FLIP_DONE;
13616e27d514SXu Han info->plane = SPRITE_PLANE;
13626e27d514SXu Han break;
13636e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
13646e27d514SXu Han info->pipe = PIPE_B;
13656e27d514SXu Han info->event = SPRITE_B_FLIP_DONE;
13666e27d514SXu Han info->plane = SPRITE_PLANE;
13676e27d514SXu Han break;
13686e27d514SXu Han case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
13696e27d514SXu Han info->pipe = PIPE_C;
13706e27d514SXu Han info->event = SPRITE_C_FLIP_DONE;
13716e27d514SXu Han info->plane = SPRITE_PLANE;
13726e27d514SXu Han break;
13736e27d514SXu Han
1374be1da707SZhi Wang default:
1375695fbc08STina Zhang gvt_vgpu_err("unknown plane code %d\n", plane);
13765c56883aSfred gao return -EBADRQC;
1377be1da707SZhi Wang }
1378be1da707SZhi Wang
1379be1da707SZhi Wang info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1380be1da707SZhi Wang info->tile_val = (dword1 & GENMASK(2, 0));
1381be1da707SZhi Wang info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1382be1da707SZhi Wang info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1383be1da707SZhi Wang
1384be30c827SJani Nikula info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
1385cd962cdbSJani Nikula info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
13869e93147fSJani Nikula info->surf_reg = DSPSURF(dev_priv, info->pipe);
1387be1da707SZhi Wang
1388be1da707SZhi Wang return 0;
1389be1da707SZhi Wang }
1390be1da707SZhi Wang
gen8_check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1391be1da707SZhi Wang static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1392be1da707SZhi Wang struct mi_display_flip_command_info *info)
1393be1da707SZhi Wang {
1394be1da707SZhi Wang u32 stride, tile;
1395be1da707SZhi Wang
1396be1da707SZhi Wang if (!info->async_flip)
1397be1da707SZhi Wang return 0;
1398be1da707SZhi Wang
1399d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) >= 9) {
140090551a12SZhenyu Wang stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
140190551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1402be1da707SZhi Wang GENMASK(12, 10)) >> 10;
1403be1da707SZhi Wang } else {
140490551a12SZhenyu Wang stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1405be1da707SZhi Wang GENMASK(15, 6)) >> 6;
140690551a12SZhenyu Wang tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1407be1da707SZhi Wang }
1408be1da707SZhi Wang
1409be1da707SZhi Wang if (stride != info->stride_val)
1410be1da707SZhi Wang gvt_dbg_cmd("cannot change stride during async flip\n");
1411be1da707SZhi Wang
1412be1da707SZhi Wang if (tile != info->tile_val)
1413be1da707SZhi Wang gvt_dbg_cmd("cannot change tile during async flip\n");
1414be1da707SZhi Wang
1415be1da707SZhi Wang return 0;
1416be1da707SZhi Wang }
1417be1da707SZhi Wang
gen8_update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1418be1da707SZhi Wang static int gen8_update_plane_mmio_from_mi_display_flip(
1419be1da707SZhi Wang struct parser_exec_state *s,
1420be1da707SZhi Wang struct mi_display_flip_command_info *info)
1421be1da707SZhi Wang {
14228fde4107SChris Wilson struct drm_i915_private *dev_priv = s->engine->i915;
1423be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu;
1424be1da707SZhi Wang
142590551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
142699c79fd4SDu, Changbin info->surf_val << 12);
1427d8d12312SLucas De Marchi if (GRAPHICS_VER(dev_priv) >= 9) {
142890551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
142999c79fd4SDu, Changbin info->stride_val);
143090551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
143199c79fd4SDu, Changbin info->tile_val << 10);
143299c79fd4SDu, Changbin } else {
143390551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
143499c79fd4SDu, Changbin info->stride_val << 6);
143590551a12SZhenyu Wang set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
143699c79fd4SDu, Changbin info->tile_val << 10);
143799c79fd4SDu, Changbin }
1438be1da707SZhi Wang
1439d39af942SColin Xu if (info->plane == PLANE_PRIMARY)
1440*2501a0b6SJani Nikula vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
1441d39af942SColin Xu
1442d39af942SColin Xu if (info->async_flip)
1443be1da707SZhi Wang intel_vgpu_trigger_virtual_event(vgpu, info->event);
1444d39af942SColin Xu else
1445d39af942SColin Xu set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1446d39af942SColin Xu
1447be1da707SZhi Wang return 0;
1448be1da707SZhi Wang }
1449be1da707SZhi Wang
decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1450be1da707SZhi Wang static int decode_mi_display_flip(struct parser_exec_state *s,
1451be1da707SZhi Wang struct mi_display_flip_command_info *info)
1452be1da707SZhi Wang {
14538fde4107SChris Wilson if (IS_BROADWELL(s->engine->i915))
1454be1da707SZhi Wang return gen8_decode_mi_display_flip(s, info);
1455d8d12312SLucas De Marchi if (GRAPHICS_VER(s->engine->i915) >= 9)
1456be1da707SZhi Wang return skl_decode_mi_display_flip(s, info);
1457be1da707SZhi Wang
1458be1da707SZhi Wang return -ENODEV;
1459be1da707SZhi Wang }
1460be1da707SZhi Wang
check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1461be1da707SZhi Wang static int check_mi_display_flip(struct parser_exec_state *s,
1462be1da707SZhi Wang struct mi_display_flip_command_info *info)
1463be1da707SZhi Wang {
1464be1da707SZhi Wang return gen8_check_mi_display_flip(s, info);
1465be1da707SZhi Wang }
1466be1da707SZhi Wang
update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1467be1da707SZhi Wang static int update_plane_mmio_from_mi_display_flip(
1468be1da707SZhi Wang struct parser_exec_state *s,
1469be1da707SZhi Wang struct mi_display_flip_command_info *info)
1470be1da707SZhi Wang {
1471be1da707SZhi Wang return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1472be1da707SZhi Wang }
1473be1da707SZhi Wang
cmd_handler_mi_display_flip(struct parser_exec_state * s)1474be1da707SZhi Wang static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1475be1da707SZhi Wang {
1476be1da707SZhi Wang struct mi_display_flip_command_info info;
1477695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1478be1da707SZhi Wang int ret;
1479be1da707SZhi Wang int i;
1480be1da707SZhi Wang int len = cmd_length(s);
148100a33be4SGao, Fred u32 valid_len = CMD_LEN(1);
148200a33be4SGao, Fred
148300a33be4SGao, Fred /* Flip Type == Stereo 3D Flip */
148400a33be4SGao, Fred if (DWORD_FIELD(2, 1, 0) == 2)
148500a33be4SGao, Fred valid_len++;
148600a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
148700a33be4SGao, Fred valid_len);
148800a33be4SGao, Fred if (ret)
148900a33be4SGao, Fred return ret;
1490be1da707SZhi Wang
1491be1da707SZhi Wang ret = decode_mi_display_flip(s, &info);
1492be1da707SZhi Wang if (ret) {
1493695fbc08STina Zhang gvt_vgpu_err("fail to decode MI display flip command\n");
1494be1da707SZhi Wang return ret;
1495be1da707SZhi Wang }
1496be1da707SZhi Wang
1497be1da707SZhi Wang ret = check_mi_display_flip(s, &info);
1498be1da707SZhi Wang if (ret) {
1499695fbc08STina Zhang gvt_vgpu_err("invalid MI display flip command\n");
1500be1da707SZhi Wang return ret;
1501be1da707SZhi Wang }
1502be1da707SZhi Wang
1503be1da707SZhi Wang ret = update_plane_mmio_from_mi_display_flip(s, &info);
1504be1da707SZhi Wang if (ret) {
1505695fbc08STina Zhang gvt_vgpu_err("fail to update plane mmio\n");
1506be1da707SZhi Wang return ret;
1507be1da707SZhi Wang }
1508be1da707SZhi Wang
1509be1da707SZhi Wang for (i = 0; i < len; i++)
1510be1da707SZhi Wang patch_value(s, cmd_ptr(s, i), MI_NOOP);
1511be1da707SZhi Wang return 0;
1512be1da707SZhi Wang }
1513be1da707SZhi Wang
is_wait_for_flip_pending(u32 cmd)1514be1da707SZhi Wang static bool is_wait_for_flip_pending(u32 cmd)
1515be1da707SZhi Wang {
1516be1da707SZhi Wang return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1517be1da707SZhi Wang MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1518be1da707SZhi Wang MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1519be1da707SZhi Wang MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1520be1da707SZhi Wang MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1521be1da707SZhi Wang MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1522be1da707SZhi Wang }
1523be1da707SZhi Wang
cmd_handler_mi_wait_for_event(struct parser_exec_state * s)1524be1da707SZhi Wang static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1525be1da707SZhi Wang {
1526be1da707SZhi Wang u32 cmd = cmd_val(s, 0);
1527be1da707SZhi Wang
1528be1da707SZhi Wang if (!is_wait_for_flip_pending(cmd))
1529be1da707SZhi Wang return 0;
1530be1da707SZhi Wang
1531be1da707SZhi Wang patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1532be1da707SZhi Wang return 0;
1533be1da707SZhi Wang }
1534be1da707SZhi Wang
get_gma_bb_from_cmd(struct parser_exec_state * s,int index)1535be1da707SZhi Wang static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1536be1da707SZhi Wang {
1537be1da707SZhi Wang unsigned long addr;
1538be1da707SZhi Wang unsigned long gma_high, gma_low;
15395c56883aSfred gao struct intel_vgpu *vgpu = s->vgpu;
15405c56883aSfred gao int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1541be1da707SZhi Wang
15425c56883aSfred gao if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
15435c56883aSfred gao gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1544be1da707SZhi Wang return INTEL_GVT_INVALID_ADDR;
15455c56883aSfred gao }
1546be1da707SZhi Wang
1547be1da707SZhi Wang gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1548be1da707SZhi Wang if (gmadr_bytes == 4) {
1549be1da707SZhi Wang addr = gma_low;
1550be1da707SZhi Wang } else {
1551be1da707SZhi Wang gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1552be1da707SZhi Wang addr = (((unsigned long)gma_high) << 32) | gma_low;
1553be1da707SZhi Wang }
1554be1da707SZhi Wang return addr;
1555be1da707SZhi Wang }
1556be1da707SZhi Wang
cmd_address_audit(struct parser_exec_state * s,unsigned long guest_gma,int op_size,bool index_mode)1557be1da707SZhi Wang static inline int cmd_address_audit(struct parser_exec_state *s,
1558be1da707SZhi Wang unsigned long guest_gma, int op_size, bool index_mode)
1559be1da707SZhi Wang {
1560be1da707SZhi Wang struct intel_vgpu *vgpu = s->vgpu;
1561be1da707SZhi Wang u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1562be1da707SZhi Wang int i;
1563be1da707SZhi Wang int ret;
1564be1da707SZhi Wang
1565be1da707SZhi Wang if (op_size > max_surface_size) {
1566695fbc08STina Zhang gvt_vgpu_err("command address audit fail name %s\n",
1567695fbc08STina Zhang s->info->name);
15685c56883aSfred gao return -EFAULT;
1569be1da707SZhi Wang }
1570be1da707SZhi Wang
1571be1da707SZhi Wang if (index_mode) {
157213bcb80bSZhenyu Wang if (guest_gma >= I915_GTT_PAGE_SIZE) {
15735c56883aSfred gao ret = -EFAULT;
1574be1da707SZhi Wang goto err;
1575be1da707SZhi Wang }
157664d8bb83SPing Gao } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
15775c56883aSfred gao ret = -EFAULT;
1578be1da707SZhi Wang goto err;
1579be1da707SZhi Wang }
158064d8bb83SPing Gao
1581be1da707SZhi Wang return 0;
158264d8bb83SPing Gao
1583be1da707SZhi Wang err:
1584695fbc08STina Zhang gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1585be1da707SZhi Wang s->info->name, guest_gma, op_size);
1586be1da707SZhi Wang
1587be1da707SZhi Wang pr_err("cmd dump: ");
1588be1da707SZhi Wang for (i = 0; i < cmd_length(s); i++) {
1589be1da707SZhi Wang if (!(i % 4))
1590be1da707SZhi Wang pr_err("\n%08x ", cmd_val(s, i));
1591be1da707SZhi Wang else
1592be1da707SZhi Wang pr_err("%08x ", cmd_val(s, i));
1593be1da707SZhi Wang }
1594be1da707SZhi Wang pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1595be1da707SZhi Wang vgpu->id,
1596be1da707SZhi Wang vgpu_aperture_gmadr_base(vgpu),
1597be1da707SZhi Wang vgpu_aperture_gmadr_end(vgpu),
1598be1da707SZhi Wang vgpu_hidden_gmadr_base(vgpu),
1599be1da707SZhi Wang vgpu_hidden_gmadr_end(vgpu));
1600be1da707SZhi Wang return ret;
1601be1da707SZhi Wang }
1602be1da707SZhi Wang
cmd_handler_mi_store_data_imm(struct parser_exec_state * s)1603be1da707SZhi Wang static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1604be1da707SZhi Wang {
1605be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1606be1da707SZhi Wang int op_size = (cmd_length(s) - 3) * sizeof(u32);
1607be1da707SZhi Wang int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1608be1da707SZhi Wang unsigned long gma, gma_low, gma_high;
160900a33be4SGao, Fred u32 valid_len = CMD_LEN(2);
1610be1da707SZhi Wang int ret = 0;
1611be1da707SZhi Wang
1612be1da707SZhi Wang /* check ppggt */
1613be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22)))
1614be1da707SZhi Wang return 0;
1615be1da707SZhi Wang
161600a33be4SGao, Fred /* check if QWORD */
161700a33be4SGao, Fred if (DWORD_FIELD(0, 21, 21))
161800a33be4SGao, Fred valid_len++;
161900a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
162000a33be4SGao, Fred valid_len);
162100a33be4SGao, Fred if (ret)
162200a33be4SGao, Fred return ret;
162300a33be4SGao, Fred
1624be1da707SZhi Wang gma = cmd_val(s, 2) & GENMASK(31, 2);
1625be1da707SZhi Wang
1626be1da707SZhi Wang if (gmadr_bytes == 8) {
1627be1da707SZhi Wang gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1628be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1629be1da707SZhi Wang gma = (gma_high << 32) | gma_low;
1630be1da707SZhi Wang core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1631be1da707SZhi Wang }
1632be1da707SZhi Wang ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1633be1da707SZhi Wang return ret;
1634be1da707SZhi Wang }
1635be1da707SZhi Wang
unexpected_cmd(struct parser_exec_state * s)1636be1da707SZhi Wang static inline int unexpected_cmd(struct parser_exec_state *s)
1637be1da707SZhi Wang {
1638695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1639695fbc08STina Zhang
1640695fbc08STina Zhang gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1641695fbc08STina Zhang
16425c56883aSfred gao return -EBADRQC;
1643be1da707SZhi Wang }
1644be1da707SZhi Wang
cmd_handler_mi_semaphore_wait(struct parser_exec_state * s)1645be1da707SZhi Wang static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1646be1da707SZhi Wang {
1647be1da707SZhi Wang return unexpected_cmd(s);
1648be1da707SZhi Wang }
1649be1da707SZhi Wang
cmd_handler_mi_report_perf_count(struct parser_exec_state * s)1650be1da707SZhi Wang static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1651be1da707SZhi Wang {
1652be1da707SZhi Wang return unexpected_cmd(s);
1653be1da707SZhi Wang }
1654be1da707SZhi Wang
cmd_handler_mi_op_2e(struct parser_exec_state * s)1655be1da707SZhi Wang static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1656be1da707SZhi Wang {
1657be1da707SZhi Wang return unexpected_cmd(s);
1658be1da707SZhi Wang }
1659be1da707SZhi Wang
cmd_handler_mi_op_2f(struct parser_exec_state * s)1660be1da707SZhi Wang static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1661be1da707SZhi Wang {
1662be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1663173bcc60SZhenyu Wang int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1664173bcc60SZhenyu Wang sizeof(u32);
1665be1da707SZhi Wang unsigned long gma, gma_high;
166600a33be4SGao, Fred u32 valid_len = CMD_LEN(1);
1667be1da707SZhi Wang int ret = 0;
1668be1da707SZhi Wang
1669be1da707SZhi Wang if (!(cmd_val(s, 0) & (1 << 22)))
1670be1da707SZhi Wang return ret;
1671be1da707SZhi Wang
167292b1aa77SZhenyu Wang /* check inline data */
167392b1aa77SZhenyu Wang if (cmd_val(s, 0) & BIT(18))
167492b1aa77SZhenyu Wang valid_len = CMD_LEN(9);
167500a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
167600a33be4SGao, Fred valid_len);
167700a33be4SGao, Fred if (ret)
167800a33be4SGao, Fred return ret;
167900a33be4SGao, Fred
1680be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 2);
1681be1da707SZhi Wang if (gmadr_bytes == 8) {
1682be1da707SZhi Wang gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1683be1da707SZhi Wang gma = (gma_high << 32) | gma;
1684be1da707SZhi Wang }
1685be1da707SZhi Wang ret = cmd_address_audit(s, gma, op_size, false);
1686be1da707SZhi Wang return ret;
1687be1da707SZhi Wang }
1688be1da707SZhi Wang
cmd_handler_mi_store_data_index(struct parser_exec_state * s)1689be1da707SZhi Wang static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1690be1da707SZhi Wang {
1691be1da707SZhi Wang return unexpected_cmd(s);
1692be1da707SZhi Wang }
1693be1da707SZhi Wang
cmd_handler_mi_clflush(struct parser_exec_state * s)1694be1da707SZhi Wang static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1695be1da707SZhi Wang {
1696be1da707SZhi Wang return unexpected_cmd(s);
1697be1da707SZhi Wang }
1698be1da707SZhi Wang
cmd_handler_mi_conditional_batch_buffer_end(struct parser_exec_state * s)1699be1da707SZhi Wang static int cmd_handler_mi_conditional_batch_buffer_end(
1700be1da707SZhi Wang struct parser_exec_state *s)
1701be1da707SZhi Wang {
1702be1da707SZhi Wang return unexpected_cmd(s);
1703be1da707SZhi Wang }
1704be1da707SZhi Wang
cmd_handler_mi_update_gtt(struct parser_exec_state * s)1705be1da707SZhi Wang static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1706be1da707SZhi Wang {
1707be1da707SZhi Wang return unexpected_cmd(s);
1708be1da707SZhi Wang }
1709be1da707SZhi Wang
cmd_handler_mi_flush_dw(struct parser_exec_state * s)1710be1da707SZhi Wang static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1711be1da707SZhi Wang {
1712be1da707SZhi Wang int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1713be1da707SZhi Wang unsigned long gma;
1714be1da707SZhi Wang bool index_mode = false;
1715be1da707SZhi Wang int ret = 0;
1716ac071578SXiaolin Zhang u32 hws_pga, val;
171700a33be4SGao, Fred u32 valid_len = CMD_LEN(2);
171800a33be4SGao, Fred
171900a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
172000a33be4SGao, Fred valid_len);
172100a33be4SGao, Fred if (ret) {
172200a33be4SGao, Fred /* Check again for Qword */
172300a33be4SGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
172400a33be4SGao, Fred ++valid_len);
172500a33be4SGao, Fred return ret;
172600a33be4SGao, Fred }
1727be1da707SZhi Wang
1728be1da707SZhi Wang /* Check post-sync and ppgtt bit */
1729be1da707SZhi Wang if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1730be1da707SZhi Wang gma = cmd_val(s, 1) & GENMASK(31, 3);
1731be1da707SZhi Wang if (gmadr_bytes == 8)
1732be1da707SZhi Wang gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1733be1da707SZhi Wang /* Store Data Index */
1734be1da707SZhi Wang if (cmd_val(s, 0) & (1 << 21))
1735be1da707SZhi Wang index_mode = true;
1736be1da707SZhi Wang ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1737ac071578SXiaolin Zhang if (ret)
1738ac071578SXiaolin Zhang return ret;
1739ac071578SXiaolin Zhang if (index_mode) {
17408fde4107SChris Wilson hws_pga = s->vgpu->hws_pga[s->engine->id];
1741ac071578SXiaolin Zhang gma = hws_pga + gma;
1742ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 1), gma);
1743ac071578SXiaolin Zhang val = cmd_val(s, 0) & (~(1 << 21));
1744ac071578SXiaolin Zhang patch_value(s, cmd_ptr(s, 0), val);
1745ac071578SXiaolin Zhang }
1746be1da707SZhi Wang }
1747be1da707SZhi Wang /* Check notify bit */
1748be1da707SZhi Wang if ((cmd_val(s, 0) & (1 << 8)))
17498fde4107SChris Wilson set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1750be1da707SZhi Wang s->workload->pending_events);
1751be1da707SZhi Wang return ret;
1752be1da707SZhi Wang }
1753be1da707SZhi Wang
addr_type_update_snb(struct parser_exec_state * s)1754be1da707SZhi Wang static void addr_type_update_snb(struct parser_exec_state *s)
1755be1da707SZhi Wang {
1756be1da707SZhi Wang if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1757be1da707SZhi Wang (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1758be1da707SZhi Wang s->buf_addr_type = PPGTT_BUFFER;
1759be1da707SZhi Wang }
1760be1da707SZhi Wang }
1761be1da707SZhi Wang
1762be1da707SZhi Wang
copy_gma_to_hva(struct intel_vgpu * vgpu,struct intel_vgpu_mm * mm,unsigned long gma,unsigned long end_gma,void * va)1763be1da707SZhi Wang static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1764be1da707SZhi Wang unsigned long gma, unsigned long end_gma, void *va)
1765be1da707SZhi Wang {
1766be1da707SZhi Wang unsigned long copy_len, offset;
1767be1da707SZhi Wang unsigned long len = 0;
1768be1da707SZhi Wang unsigned long gpa;
1769be1da707SZhi Wang
1770be1da707SZhi Wang while (gma != end_gma) {
1771be1da707SZhi Wang gpa = intel_vgpu_gma_to_gpa(mm, gma);
1772be1da707SZhi Wang if (gpa == INTEL_GVT_INVALID_ADDR) {
1773695fbc08STina Zhang gvt_vgpu_err("invalid gma address: %lx\n", gma);
1774be1da707SZhi Wang return -EFAULT;
1775be1da707SZhi Wang }
1776be1da707SZhi Wang
17779556e118SZhi Wang offset = gma & (I915_GTT_PAGE_SIZE - 1);
1778be1da707SZhi Wang
17799556e118SZhi Wang copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
17809556e118SZhi Wang I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1781be1da707SZhi Wang
1782e3d7640eSChristoph Hellwig intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1783be1da707SZhi Wang
1784be1da707SZhi Wang len += copy_len;
1785be1da707SZhi Wang gma += copy_len;
1786be1da707SZhi Wang }
178773dec95eSTvrtko Ursulin return len;
1788be1da707SZhi Wang }
1789be1da707SZhi Wang
1790be1da707SZhi Wang
1791be1da707SZhi Wang /*
1792be1da707SZhi Wang * Check whether a batch buffer needs to be scanned. Currently
1793be1da707SZhi Wang * the only criteria is based on privilege.
1794be1da707SZhi Wang */
batch_buffer_needs_scan(struct parser_exec_state * s)1795be1da707SZhi Wang static int batch_buffer_needs_scan(struct parser_exec_state *s)
1796be1da707SZhi Wang {
1797f093f182SColin Xu /* Decide privilege based on address space */
17988fde4107SChris Wilson if (cmd_val(s, 0) & BIT(8) &&
17998fde4107SChris Wilson !(s->vgpu->scan_nonprivbb & s->engine->mask))
1800be1da707SZhi Wang return 0;
18018fde4107SChris Wilson
1802be1da707SZhi Wang return 1;
1803be1da707SZhi Wang }
1804be1da707SZhi Wang
repr_addr_type(unsigned int type)18058fde4107SChris Wilson static const char *repr_addr_type(unsigned int type)
18068fde4107SChris Wilson {
18078fde4107SChris Wilson return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
18088fde4107SChris Wilson }
18098fde4107SChris Wilson
find_bb_size(struct parser_exec_state * s,unsigned long * bb_size,unsigned long * bb_end_cmd_offset)1810220b65d8STina Zhang static int find_bb_size(struct parser_exec_state *s,
1811220b65d8STina Zhang unsigned long *bb_size,
1812220b65d8STina Zhang unsigned long *bb_end_cmd_offset)
1813be1da707SZhi Wang {
1814be1da707SZhi Wang unsigned long gma = 0;
1815b007065aSJani Nikula const struct cmd_info *info;
18162e679d48SJani Nikula u32 cmd_len = 0;
181758facf8cSZhi Wang bool bb_end = false;
1818695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1819be1da707SZhi Wang u32 cmd;
182096bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
182196bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1822be1da707SZhi Wang
182358facf8cSZhi Wang *bb_size = 0;
1824220b65d8STina Zhang *bb_end_cmd_offset = 0;
182558facf8cSZhi Wang
1826be1da707SZhi Wang /* get the start gm address of the batch buffer */
1827be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1);
18285c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR)
18295c56883aSfred gao return -EFAULT;
18305c56883aSfred gao
1831be1da707SZhi Wang cmd = cmd_val(s, 0);
18328fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1833be1da707SZhi Wang if (info == NULL) {
18348fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
18358fde4107SChris Wilson cmd, get_opcode(cmd, s->engine),
18368fde4107SChris Wilson repr_addr_type(s->buf_addr_type),
18378fde4107SChris Wilson s->engine->name, s->workload);
18385c56883aSfred gao return -EBADRQC;
1839be1da707SZhi Wang }
1840be1da707SZhi Wang do {
184196bebe39SZhao Yan if (copy_gma_to_hva(s->vgpu, mm,
18425c56883aSfred gao gma, gma + 4, &cmd) < 0)
18435c56883aSfred gao return -EFAULT;
18448fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1845be1da707SZhi Wang if (info == NULL) {
18468fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
18478fde4107SChris Wilson cmd, get_opcode(cmd, s->engine),
18488fde4107SChris Wilson repr_addr_type(s->buf_addr_type),
18498fde4107SChris Wilson s->engine->name, s->workload);
18505c56883aSfred gao return -EBADRQC;
1851be1da707SZhi Wang }
1852be1da707SZhi Wang
1853be1da707SZhi Wang if (info->opcode == OP_MI_BATCH_BUFFER_END) {
185458facf8cSZhi Wang bb_end = true;
1855be1da707SZhi Wang } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
185658facf8cSZhi Wang if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1857be1da707SZhi Wang /* chained batch buffer */
185858facf8cSZhi Wang bb_end = true;
1859be1da707SZhi Wang }
1860220b65d8STina Zhang
1861220b65d8STina Zhang if (bb_end)
1862220b65d8STina Zhang *bb_end_cmd_offset = *bb_size;
1863220b65d8STina Zhang
1864be1da707SZhi Wang cmd_len = get_cmd_length(info, cmd) << 2;
186558facf8cSZhi Wang *bb_size += cmd_len;
1866be1da707SZhi Wang gma += cmd_len;
186758facf8cSZhi Wang } while (!bb_end);
1868be1da707SZhi Wang
186958facf8cSZhi Wang return 0;
1870be1da707SZhi Wang }
1871be1da707SZhi Wang
audit_bb_end(struct parser_exec_state * s,void * va)1872220b65d8STina Zhang static int audit_bb_end(struct parser_exec_state *s, void *va)
1873220b65d8STina Zhang {
1874220b65d8STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1875220b65d8STina Zhang u32 cmd = *(u32 *)va;
1876220b65d8STina Zhang const struct cmd_info *info;
1877220b65d8STina Zhang
18788fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1879220b65d8STina Zhang if (info == NULL) {
18808fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
18818fde4107SChris Wilson cmd, get_opcode(cmd, s->engine),
18828fde4107SChris Wilson repr_addr_type(s->buf_addr_type),
18838fde4107SChris Wilson s->engine->name, s->workload);
1884220b65d8STina Zhang return -EBADRQC;
1885220b65d8STina Zhang }
1886220b65d8STina Zhang
1887220b65d8STina Zhang if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1888220b65d8STina Zhang ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1889220b65d8STina Zhang (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1890220b65d8STina Zhang return 0;
1891220b65d8STina Zhang
1892220b65d8STina Zhang return -EBADRQC;
1893220b65d8STina Zhang }
1894220b65d8STina Zhang
perform_bb_shadow(struct parser_exec_state * s)1895be1da707SZhi Wang static int perform_bb_shadow(struct parser_exec_state *s)
1896be1da707SZhi Wang {
1897695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1898f52c380aSZhi Wang struct intel_vgpu_shadow_bb *bb;
1899be1da707SZhi Wang unsigned long gma = 0;
190058facf8cSZhi Wang unsigned long bb_size;
1901220b65d8STina Zhang unsigned long bb_end_cmd_offset;
1902be1da707SZhi Wang int ret = 0;
190396bebe39SZhao Yan struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
190496bebe39SZhao Yan s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
19058475355fSChris Wilson unsigned long start_offset = 0;
1906be1da707SZhi Wang
1907be1da707SZhi Wang /* get the start gm address of the batch buffer */
1908be1da707SZhi Wang gma = get_gma_bb_from_cmd(s, 1);
19095c56883aSfred gao if (gma == INTEL_GVT_INVALID_ADDR)
19105c56883aSfred gao return -EFAULT;
1911be1da707SZhi Wang
1912220b65d8STina Zhang ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
191358facf8cSZhi Wang if (ret)
191458facf8cSZhi Wang return ret;
1915be1da707SZhi Wang
1916f52c380aSZhi Wang bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1917f52c380aSZhi Wang if (!bb)
1918be1da707SZhi Wang return -ENOMEM;
1919be1da707SZhi Wang
192096bebe39SZhao Yan bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
192196bebe39SZhao Yan
19228475355fSChris Wilson /* the start_offset stores the batch buffer's start gma's
192396bebe39SZhao Yan * offset relative to page boundary. so for non-privileged batch
192496bebe39SZhao Yan * buffer, the shadowed gem object holds exactly the same page
192596bebe39SZhao Yan * layout as original gem object. This is for the convience of
192696bebe39SZhao Yan * replacing the whole non-privilged batch buffer page to this
192796bebe39SZhao Yan * shadowed one in PPGTT at the same gma address. (this replacing
192896bebe39SZhao Yan * action is not implemented yet now, but may be necessary in
192996bebe39SZhao Yan * future).
193096bebe39SZhao Yan * for prileged batch buffer, we just change start gma address to
193196bebe39SZhao Yan * that of shadowed page.
193296bebe39SZhao Yan */
193396bebe39SZhao Yan if (bb->ppgtt)
19348475355fSChris Wilson start_offset = gma & ~I915_GTT_PAGE_MASK;
193596bebe39SZhao Yan
19368fde4107SChris Wilson bb->obj = i915_gem_object_create_shmem(s->engine->i915,
19378475355fSChris Wilson round_up(bb_size + start_offset,
19388475355fSChris Wilson PAGE_SIZE));
1939f52c380aSZhi Wang if (IS_ERR(bb->obj)) {
1940f52c380aSZhi Wang ret = PTR_ERR(bb->obj);
1941f52c380aSZhi Wang goto err_free_bb;
1942be1da707SZhi Wang }
1943be1da707SZhi Wang
1944f52c380aSZhi Wang bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1945f52c380aSZhi Wang if (IS_ERR(bb->va)) {
1946f52c380aSZhi Wang ret = PTR_ERR(bb->va);
1947033ef711SChris Wilson goto err_free_obj;
1948f52c380aSZhi Wang }
1949be1da707SZhi Wang
195096bebe39SZhao Yan ret = copy_gma_to_hva(s->vgpu, mm,
1951a2861504SChris Wilson gma, gma + bb_size,
19528475355fSChris Wilson bb->va + start_offset);
19538bcad07aSZhenyu Wang if (ret < 0) {
1954695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n");
1955f52c380aSZhi Wang ret = -EFAULT;
1956f52c380aSZhi Wang goto err_unmap;
1957be1da707SZhi Wang }
1958be1da707SZhi Wang
1959220b65d8STina Zhang ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1960220b65d8STina Zhang if (ret)
1961220b65d8STina Zhang goto err_unmap;
1962220b65d8STina Zhang
19631af343cdSMaarten Lankhorst i915_gem_object_unlock(bb->obj);
1964f52c380aSZhi Wang INIT_LIST_HEAD(&bb->list);
1965f52c380aSZhi Wang list_add(&bb->list, &s->workload->shadow_bb);
1966f52c380aSZhi Wang
1967f52c380aSZhi Wang bb->bb_start_cmd_va = s->ip_va;
1968f52c380aSZhi Wang
1969ef75c685Sfred gao if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1970ef75c685Sfred gao bb->bb_offset = s->ip_va - s->rb_va;
1971ef75c685Sfred gao else
1972ef75c685Sfred gao bb->bb_offset = 0;
1973ef75c685Sfred gao
1974be1da707SZhi Wang /*
1975be1da707SZhi Wang * ip_va saves the virtual address of the shadow batch buffer, while
1976be1da707SZhi Wang * ip_gma saves the graphics address of the original batch buffer.
1977be1da707SZhi Wang * As the shadow batch buffer is just a copy from the originial one,
1978be1da707SZhi Wang * it should be right to use shadow batch buffer'va and original batch
1979be1da707SZhi Wang * buffer's gma in pair. After all, we don't want to pin the shadow
1980be1da707SZhi Wang * buffer here (too early).
1981be1da707SZhi Wang */
19828475355fSChris Wilson s->ip_va = bb->va + start_offset;
1983be1da707SZhi Wang s->ip_gma = gma;
1984be1da707SZhi Wang return 0;
1985f52c380aSZhi Wang err_unmap:
1986f52c380aSZhi Wang i915_gem_object_unpin_map(bb->obj);
1987f52c380aSZhi Wang err_free_obj:
1988f52c380aSZhi Wang i915_gem_object_put(bb->obj);
1989f52c380aSZhi Wang err_free_bb:
1990f52c380aSZhi Wang kfree(bb);
1991be1da707SZhi Wang return ret;
1992be1da707SZhi Wang }
1993be1da707SZhi Wang
cmd_handler_mi_batch_buffer_start(struct parser_exec_state * s)1994be1da707SZhi Wang static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1995be1da707SZhi Wang {
1996be1da707SZhi Wang bool second_level;
1997be1da707SZhi Wang int ret = 0;
1998695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
1999be1da707SZhi Wang
2000be1da707SZhi Wang if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
2001695fbc08STina Zhang gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
20025c56883aSfred gao return -EFAULT;
2003be1da707SZhi Wang }
2004be1da707SZhi Wang
2005be1da707SZhi Wang second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2006be1da707SZhi Wang if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2007695fbc08STina Zhang gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
20085c56883aSfred gao return -EFAULT;
2009be1da707SZhi Wang }
2010be1da707SZhi Wang
2011be1da707SZhi Wang s->saved_buf_addr_type = s->buf_addr_type;
2012be1da707SZhi Wang addr_type_update_snb(s);
2013be1da707SZhi Wang if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2014be1da707SZhi Wang s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2015be1da707SZhi Wang s->buf_type = BATCH_BUFFER_INSTRUCTION;
2016be1da707SZhi Wang } else if (second_level) {
2017be1da707SZhi Wang s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2018be1da707SZhi Wang s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2019be1da707SZhi Wang s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2020be1da707SZhi Wang }
2021be1da707SZhi Wang
2022be1da707SZhi Wang if (batch_buffer_needs_scan(s)) {
2023be1da707SZhi Wang ret = perform_bb_shadow(s);
2024be1da707SZhi Wang if (ret < 0)
2025695fbc08STina Zhang gvt_vgpu_err("invalid shadow batch buffer\n");
2026be1da707SZhi Wang } else {
2027be1da707SZhi Wang /* emulate a batch buffer end to do return right */
2028be1da707SZhi Wang ret = cmd_handler_mi_batch_buffer_end(s);
2029be1da707SZhi Wang if (ret < 0)
2030be1da707SZhi Wang return ret;
2031be1da707SZhi Wang }
2032be1da707SZhi Wang return ret;
2033be1da707SZhi Wang }
2034be1da707SZhi Wang
2035db47685dSZhao Yan static int mi_noop_index;
2036db47685dSZhao Yan
2037b007065aSJani Nikula static const struct cmd_info cmd_info[] = {
2038be1da707SZhi Wang {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2039be1da707SZhi Wang
2040be1da707SZhi Wang {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2041be1da707SZhi Wang 0, 1, NULL},
2042be1da707SZhi Wang
2043be1da707SZhi Wang {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2044be1da707SZhi Wang 0, 1, cmd_handler_mi_user_interrupt},
2045be1da707SZhi Wang
2046be1da707SZhi Wang {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2047be1da707SZhi Wang D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2048be1da707SZhi Wang
2049be1da707SZhi Wang {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2050be1da707SZhi Wang
2051be1da707SZhi Wang {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2052be1da707SZhi Wang NULL},
2053be1da707SZhi Wang
2054be1da707SZhi Wang {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2055be1da707SZhi Wang NULL},
2056be1da707SZhi Wang
2057be1da707SZhi Wang {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2058be1da707SZhi Wang NULL},
2059be1da707SZhi Wang
2060be1da707SZhi Wang {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2061be1da707SZhi Wang NULL},
2062be1da707SZhi Wang
2063be1da707SZhi Wang {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2064be1da707SZhi Wang D_ALL, 0, 1, NULL},
2065be1da707SZhi Wang
2066be1da707SZhi Wang {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2067be1da707SZhi Wang F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2068be1da707SZhi Wang cmd_handler_mi_batch_buffer_end},
2069be1da707SZhi Wang
2070be1da707SZhi Wang {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2071be1da707SZhi Wang 0, 1, NULL},
2072be1da707SZhi Wang
2073be1da707SZhi Wang {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2074be1da707SZhi Wang NULL},
2075be1da707SZhi Wang
2076be1da707SZhi Wang {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2077be1da707SZhi Wang D_ALL, 0, 1, NULL},
2078be1da707SZhi Wang
2079be1da707SZhi Wang {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2080be1da707SZhi Wang NULL},
2081be1da707SZhi Wang
2082be1da707SZhi Wang {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2083be1da707SZhi Wang NULL},
2084be1da707SZhi Wang
20854f870f1fSGao, Fred {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2086be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2087be1da707SZhi Wang
20881e2adc0dSGao, Fred {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
20891e2adc0dSGao, Fred R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2090be1da707SZhi Wang
2091be1da707SZhi Wang {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2092be1da707SZhi Wang
20931e2adc0dSGao, Fred {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
20941e2adc0dSGao, Fred D_ALL, 0, 8, NULL, CMD_LEN(0)},
2095be1da707SZhi Wang
20961e2adc0dSGao, Fred {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
20971e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
20981e2adc0dSGao, Fred NULL, CMD_LEN(0)},
2099be1da707SZhi Wang
21001e2adc0dSGao, Fred {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
21011e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
21021e2adc0dSGao, Fred 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2103be1da707SZhi Wang
2104be1da707SZhi Wang {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2105be1da707SZhi Wang ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2106be1da707SZhi Wang
2107be1da707SZhi Wang {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2108be1da707SZhi Wang 0, 8, cmd_handler_mi_store_data_index},
2109be1da707SZhi Wang
2110be1da707SZhi Wang {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2111be1da707SZhi Wang D_ALL, 0, 8, cmd_handler_lri},
2112be1da707SZhi Wang
2113be1da707SZhi Wang {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2114be1da707SZhi Wang cmd_handler_mi_update_gtt},
2115be1da707SZhi Wang
21161e2adc0dSGao, Fred {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
21171e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
21181e2adc0dSGao, Fred cmd_handler_srm, CMD_LEN(2)},
2119be1da707SZhi Wang
2120be1da707SZhi Wang {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2121be1da707SZhi Wang cmd_handler_mi_flush_dw},
2122be1da707SZhi Wang
2123be1da707SZhi Wang {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2124be1da707SZhi Wang 10, cmd_handler_mi_clflush},
2125be1da707SZhi Wang
21261e2adc0dSGao, Fred {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
21271e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
21281e2adc0dSGao, Fred cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2129be1da707SZhi Wang
21301e2adc0dSGao, Fred {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
21311e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
21321e2adc0dSGao, Fred cmd_handler_lrm, CMD_LEN(2)},
2133be1da707SZhi Wang
21341e2adc0dSGao, Fred {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
21351e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
21361e2adc0dSGao, Fred cmd_handler_lrr, CMD_LEN(1)},
2137be1da707SZhi Wang
21381e2adc0dSGao, Fred {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
21391e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
21401e2adc0dSGao, Fred 8, NULL, CMD_LEN(2)},
2141be1da707SZhi Wang
21421e2adc0dSGao, Fred {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
21431e2adc0dSGao, Fred R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2144be1da707SZhi Wang
2145be1da707SZhi Wang {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2146be1da707SZhi Wang ADDR_FIX_1(2), 8, NULL},
2147be1da707SZhi Wang
21481e2adc0dSGao, Fred {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
21491e2adc0dSGao, Fred ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2150be1da707SZhi Wang
2151be1da707SZhi Wang {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2152be1da707SZhi Wang 8, cmd_handler_mi_op_2f},
2153be1da707SZhi Wang
2154be1da707SZhi Wang {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2155be1da707SZhi Wang F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2156be1da707SZhi Wang cmd_handler_mi_batch_buffer_start},
2157be1da707SZhi Wang
2158be1da707SZhi Wang {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
21591e2adc0dSGao, Fred F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
21601e2adc0dSGao, Fred cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2161be1da707SZhi Wang
2162be1da707SZhi Wang {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2163be1da707SZhi Wang R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2164be1da707SZhi Wang
2165be1da707SZhi Wang {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2166be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL},
2167be1da707SZhi Wang
2168be1da707SZhi Wang {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2169be1da707SZhi Wang 0, 8, NULL},
2170be1da707SZhi Wang
2171be1da707SZhi Wang {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2172be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2173be1da707SZhi Wang
2174be1da707SZhi Wang {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2175be1da707SZhi Wang
2176be1da707SZhi Wang {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2177be1da707SZhi Wang 0, 8, NULL},
2178be1da707SZhi Wang
2179be1da707SZhi Wang {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2180be1da707SZhi Wang ADDR_FIX_1(3), 8, NULL},
2181be1da707SZhi Wang
2182be1da707SZhi Wang {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2183be1da707SZhi Wang D_ALL, 0, 8, NULL},
2184be1da707SZhi Wang
2185be1da707SZhi Wang {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2186be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL},
2187be1da707SZhi Wang
2188be1da707SZhi Wang {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2189be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL},
2190be1da707SZhi Wang
2191be1da707SZhi Wang {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2192be1da707SZhi Wang ADDR_FIX_1(4), 8, NULL},
2193be1da707SZhi Wang
2194be1da707SZhi Wang {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2195be1da707SZhi Wang ADDR_FIX_2(4, 7), 8, NULL},
2196be1da707SZhi Wang
2197be1da707SZhi Wang {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2198be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2199be1da707SZhi Wang
2200be1da707SZhi Wang {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2201be1da707SZhi Wang
2202be1da707SZhi Wang {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2203be1da707SZhi Wang D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2204be1da707SZhi Wang
2205be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2206be1da707SZhi Wang R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2207be1da707SZhi Wang
2208be1da707SZhi Wang {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2209be1da707SZhi Wang OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2210be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2211be1da707SZhi Wang
2212be1da707SZhi Wang {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2213be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL},
2214be1da707SZhi Wang
2215be1da707SZhi Wang {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2216be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2217be1da707SZhi Wang
2218be1da707SZhi Wang {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2219be1da707SZhi Wang D_ALL, ADDR_FIX_1(4), 8, NULL},
2220be1da707SZhi Wang
2221be1da707SZhi Wang {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2222be1da707SZhi Wang D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2223be1da707SZhi Wang
2224be1da707SZhi Wang {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2225be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2226be1da707SZhi Wang
2227be1da707SZhi Wang {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2228be1da707SZhi Wang OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2229be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2230be1da707SZhi Wang
2231be1da707SZhi Wang {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2232be1da707SZhi Wang ADDR_FIX_2(4, 5), 8, NULL},
2233be1da707SZhi Wang
2234be1da707SZhi Wang {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2235be1da707SZhi Wang F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2236be1da707SZhi Wang
2237be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2238be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2239be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2240be1da707SZhi Wang
2241be1da707SZhi Wang {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2242be1da707SZhi Wang OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2243be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2244be1da707SZhi Wang
2245be1da707SZhi Wang {"3DSTATE_BLEND_STATE_POINTERS",
2246be1da707SZhi Wang OP_3DSTATE_BLEND_STATE_POINTERS,
2247be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248be1da707SZhi Wang
2249be1da707SZhi Wang {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2250be1da707SZhi Wang OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2251be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2252be1da707SZhi Wang
2253be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2254be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2255be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2256be1da707SZhi Wang
2257be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2258be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2259be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2260be1da707SZhi Wang
2261be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2262be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2263be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2264be1da707SZhi Wang
2265be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2266be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2267be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2268be1da707SZhi Wang
2269be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2270be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2271be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272be1da707SZhi Wang
2273be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2274be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2275be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2276be1da707SZhi Wang
2277be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2278be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2279be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2280be1da707SZhi Wang
2281be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2282be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2283be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284be1da707SZhi Wang
2285be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2286be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2287be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2288be1da707SZhi Wang
2289be1da707SZhi Wang {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2290be1da707SZhi Wang OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2291be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2292be1da707SZhi Wang
2293be1da707SZhi Wang {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2294be1da707SZhi Wang 0, 8, NULL},
2295be1da707SZhi Wang
2296be1da707SZhi Wang {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2297be1da707SZhi Wang 0, 8, NULL},
2298be1da707SZhi Wang
2299be1da707SZhi Wang {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2300be1da707SZhi Wang 0, 8, NULL},
2301be1da707SZhi Wang
2302be1da707SZhi Wang {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2303be1da707SZhi Wang 0, 8, NULL},
2304be1da707SZhi Wang
2305be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2306be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2307be1da707SZhi Wang
2308be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2309be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2310be1da707SZhi Wang
2311be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2312be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2313be1da707SZhi Wang
2314be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2315be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316be1da707SZhi Wang
2317be1da707SZhi Wang {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2318be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2319be1da707SZhi Wang
2320be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2321be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2322be1da707SZhi Wang
2323be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2324be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2325be1da707SZhi Wang
2326be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2327be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2328be1da707SZhi Wang
2329be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2330be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2331be1da707SZhi Wang
2332be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2333be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2334be1da707SZhi Wang
2335be1da707SZhi Wang {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2336be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2337be1da707SZhi Wang
2338be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2339be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2340be1da707SZhi Wang
2341be1da707SZhi Wang {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2342be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343be1da707SZhi Wang
2344be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2345be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2346be1da707SZhi Wang
2347be1da707SZhi Wang {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2348be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349be1da707SZhi Wang
2350be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2351be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2352be1da707SZhi Wang
2353be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2354be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2355be1da707SZhi Wang
2356be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2357be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2358be1da707SZhi Wang
2359be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2360be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2361be1da707SZhi Wang
2362be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2363be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2364be1da707SZhi Wang
2365be1da707SZhi Wang {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2366be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2367be1da707SZhi Wang
2368be1da707SZhi Wang {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2369be1da707SZhi Wang NULL},
2370be1da707SZhi Wang
2371be1da707SZhi Wang {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2372be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2373be1da707SZhi Wang
2374be1da707SZhi Wang {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2375be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2376be1da707SZhi Wang
2377be1da707SZhi Wang {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2378be1da707SZhi Wang 8, NULL},
2379be1da707SZhi Wang
2380be1da707SZhi Wang {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2381be1da707SZhi Wang R_RCS, D_BDW_PLUS, 0, 8, NULL},
2382be1da707SZhi Wang
2383be1da707SZhi Wang {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2384be1da707SZhi Wang 8, NULL},
2385be1da707SZhi Wang
2386be1da707SZhi Wang {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2387be1da707SZhi Wang NULL},
2388be1da707SZhi Wang
2389be1da707SZhi Wang {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2390be1da707SZhi Wang NULL},
2391be1da707SZhi Wang
2392be1da707SZhi Wang {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2393be1da707SZhi Wang NULL},
2394be1da707SZhi Wang
2395be1da707SZhi Wang {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2396be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2397be1da707SZhi Wang
2398be1da707SZhi Wang {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2399be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL},
2400be1da707SZhi Wang
2401be1da707SZhi Wang {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2402be1da707SZhi Wang D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2403be1da707SZhi Wang
2404be1da707SZhi Wang {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2405be1da707SZhi Wang R_RCS, D_ALL, 0, 1, NULL},
2406be1da707SZhi Wang
2407be1da707SZhi Wang {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2408be1da707SZhi Wang
2409be1da707SZhi Wang {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2410be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL},
2411be1da707SZhi Wang
2412be1da707SZhi Wang {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2413be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2414be1da707SZhi Wang
2415be1da707SZhi Wang {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2416be1da707SZhi Wang
2417be1da707SZhi Wang {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2418be1da707SZhi Wang
2419be1da707SZhi Wang {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2420be1da707SZhi Wang
2421be1da707SZhi Wang {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2422be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2423be1da707SZhi Wang
2424be1da707SZhi Wang {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2425be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2426be1da707SZhi Wang
2427be1da707SZhi Wang {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2428be1da707SZhi Wang D_ALL, 0, 8, NULL},
2429be1da707SZhi Wang
2430be1da707SZhi Wang {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2431be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2432be1da707SZhi Wang
2433be1da707SZhi Wang {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2434be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2435be1da707SZhi Wang
2436be1da707SZhi Wang {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2437be1da707SZhi Wang
2438be1da707SZhi Wang {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2439be1da707SZhi Wang
2440be1da707SZhi Wang {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2441be1da707SZhi Wang
2442be1da707SZhi Wang {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2443be1da707SZhi Wang D_ALL, 0, 8, NULL},
2444be1da707SZhi Wang
2445be1da707SZhi Wang {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2446be1da707SZhi Wang
2447be1da707SZhi Wang {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2448be1da707SZhi Wang
2449be1da707SZhi Wang {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2450be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL},
2451be1da707SZhi Wang
2452be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2453be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2454be1da707SZhi Wang
2455be1da707SZhi Wang {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2456be1da707SZhi Wang 0, 8, NULL},
2457be1da707SZhi Wang
2458be1da707SZhi Wang {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2459be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL},
2460be1da707SZhi Wang
2461be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2462be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2463be1da707SZhi Wang
2464be1da707SZhi Wang {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2465be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2466be1da707SZhi Wang
2467be1da707SZhi Wang {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2468be1da707SZhi Wang D_ALL, 0, 8, NULL},
2469be1da707SZhi Wang
2470be1da707SZhi Wang {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2471be1da707SZhi Wang D_ALL, 0, 8, NULL},
2472be1da707SZhi Wang
2473be1da707SZhi Wang {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2474be1da707SZhi Wang D_ALL, 0, 8, NULL},
2475be1da707SZhi Wang
2476be1da707SZhi Wang {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2477be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2478be1da707SZhi Wang
2479be1da707SZhi Wang {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2480be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2481be1da707SZhi Wang
2482be1da707SZhi Wang {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2483be1da707SZhi Wang D_ALL, ADDR_FIX_1(2), 8, NULL},
2484be1da707SZhi Wang
2485be1da707SZhi Wang {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2486be1da707SZhi Wang R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2487be1da707SZhi Wang
2488be1da707SZhi Wang {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2489be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL},
2490be1da707SZhi Wang
2491be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2492be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2493be1da707SZhi Wang
2494be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2495be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2496be1da707SZhi Wang
2497be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2498be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2499be1da707SZhi Wang
2500be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2501be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2502be1da707SZhi Wang
2503be1da707SZhi Wang {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2504be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2505be1da707SZhi Wang
2506be1da707SZhi Wang {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2507be1da707SZhi Wang R_RCS, D_ALL, 0, 8, NULL},
2508be1da707SZhi Wang
2509be1da707SZhi Wang {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2510be1da707SZhi Wang D_ALL, 0, 9, NULL},
2511be1da707SZhi Wang
2512be1da707SZhi Wang {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2513be1da707SZhi Wang ADDR_FIX_2(2, 4), 8, NULL},
2514be1da707SZhi Wang
2515be1da707SZhi Wang {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2516be1da707SZhi Wang OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2517be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2518be1da707SZhi Wang
2519be1da707SZhi Wang {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2520be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2521be1da707SZhi Wang
2522be1da707SZhi Wang {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2523be1da707SZhi Wang OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2524be1da707SZhi Wang F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2525be1da707SZhi Wang
2526be1da707SZhi Wang {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2527be1da707SZhi Wang D_BDW_PLUS, 0, 8, NULL},
2528be1da707SZhi Wang
2529be1da707SZhi Wang {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2530be1da707SZhi Wang ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2531be1da707SZhi Wang
2532be1da707SZhi Wang {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2533be1da707SZhi Wang
2534be1da707SZhi Wang {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2535be1da707SZhi Wang 1, NULL},
2536be1da707SZhi Wang
2537be1da707SZhi Wang {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2538be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL},
2539be1da707SZhi Wang
2540be1da707SZhi Wang {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2541be1da707SZhi Wang
2542be1da707SZhi Wang {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2543be1da707SZhi Wang ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2544be1da707SZhi Wang
2545be1da707SZhi Wang {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2546be1da707SZhi Wang ADDR_FIX_1(1), 8, NULL},
2547be1da707SZhi Wang
25482484b172SYan Zhao {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
25492484b172SYan Zhao F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
25502484b172SYan Zhao
2551be1da707SZhi Wang {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2552be1da707SZhi Wang
2553be1da707SZhi Wang {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2554be1da707SZhi Wang
2555be1da707SZhi Wang {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2556be1da707SZhi Wang 0, 8, NULL},
2557be1da707SZhi Wang
2558be1da707SZhi Wang {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2559be1da707SZhi Wang D_SKL_PLUS, 0, 8, NULL},
2560be1da707SZhi Wang
2561be1da707SZhi Wang {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2562be1da707SZhi Wang F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2563be1da707SZhi Wang
2564be1da707SZhi Wang {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2565be1da707SZhi Wang 0, 16, NULL},
2566be1da707SZhi Wang
2567be1da707SZhi Wang {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2568be1da707SZhi Wang 0, 16, NULL},
2569be1da707SZhi Wang
257002b966c1SColin Xu {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
257102b966c1SColin Xu 0, 16, NULL},
257202b966c1SColin Xu
2573be1da707SZhi Wang {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2574be1da707SZhi Wang
2575be1da707SZhi Wang {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2576be1da707SZhi Wang 0, 16, NULL},
2577be1da707SZhi Wang
2578be1da707SZhi Wang {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2579be1da707SZhi Wang 0, 16, NULL},
2580be1da707SZhi Wang
2581be1da707SZhi Wang {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2582be1da707SZhi Wang 0, 16, NULL},
2583be1da707SZhi Wang
2584be1da707SZhi Wang {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2585be1da707SZhi Wang 0, 8, NULL},
2586be1da707SZhi Wang
2587be1da707SZhi Wang {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2588be1da707SZhi Wang NULL},
2589be1da707SZhi Wang
2590be1da707SZhi Wang {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2591be1da707SZhi Wang F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2592be1da707SZhi Wang
2593be1da707SZhi Wang {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2594be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2595be1da707SZhi Wang
2596be1da707SZhi Wang {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2597be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2598be1da707SZhi Wang
2599be1da707SZhi Wang {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2600be1da707SZhi Wang R_VCS, D_BDW_PLUS, 0, 12, NULL},
2601be1da707SZhi Wang
2602be1da707SZhi Wang {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2603be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2604be1da707SZhi Wang
2605be1da707SZhi Wang {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2606be1da707SZhi Wang F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2607be1da707SZhi Wang
2608be1da707SZhi Wang {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2609be1da707SZhi Wang
2610be1da707SZhi Wang {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2611be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2612be1da707SZhi Wang
2613be1da707SZhi Wang {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2614be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2615be1da707SZhi Wang
2616be1da707SZhi Wang {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2617be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2618be1da707SZhi Wang
2619be1da707SZhi Wang {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2620be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2621be1da707SZhi Wang
2622be1da707SZhi Wang {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2623be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2624be1da707SZhi Wang
2625be1da707SZhi Wang {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2626be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2627be1da707SZhi Wang
2628be1da707SZhi Wang {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2629be1da707SZhi Wang R_VCS, D_ALL, 0, 6, NULL},
2630be1da707SZhi Wang
2631be1da707SZhi Wang {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2632be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2633be1da707SZhi Wang
2634be1da707SZhi Wang {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2635be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2636be1da707SZhi Wang
2637be1da707SZhi Wang {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2638be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2639be1da707SZhi Wang
2640be1da707SZhi Wang {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2641be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2642be1da707SZhi Wang
2643be1da707SZhi Wang {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2644be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2645be1da707SZhi Wang
2646be1da707SZhi Wang {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2647be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2648be1da707SZhi Wang
2649be1da707SZhi Wang {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2650be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2651be1da707SZhi Wang {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2652be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2653be1da707SZhi Wang
2654be1da707SZhi Wang {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2655be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2656be1da707SZhi Wang
2657be1da707SZhi Wang {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2658be1da707SZhi Wang R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2659be1da707SZhi Wang
2660be1da707SZhi Wang {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2661be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2662be1da707SZhi Wang
2663be1da707SZhi Wang {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2664be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2665be1da707SZhi Wang
2666be1da707SZhi Wang {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2667be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2668be1da707SZhi Wang
2669be1da707SZhi Wang {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2670be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2671be1da707SZhi Wang
2672be1da707SZhi Wang {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2673be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2674be1da707SZhi Wang
2675be1da707SZhi Wang {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2676be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2677be1da707SZhi Wang
2678be1da707SZhi Wang {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2679be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2680be1da707SZhi Wang
2681be1da707SZhi Wang {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2682be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2683be1da707SZhi Wang
2684be1da707SZhi Wang {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2685be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2686be1da707SZhi Wang
2687be1da707SZhi Wang {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2688be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2689be1da707SZhi Wang
2690be1da707SZhi Wang {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2691be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2692be1da707SZhi Wang
2693be1da707SZhi Wang {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2694be1da707SZhi Wang 0, 16, NULL},
2695be1da707SZhi Wang
2696be1da707SZhi Wang {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2697be1da707SZhi Wang
2698be1da707SZhi Wang {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2699be1da707SZhi Wang
2700be1da707SZhi Wang {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2701be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2702be1da707SZhi Wang
2703be1da707SZhi Wang {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2704be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2705be1da707SZhi Wang
2706be1da707SZhi Wang {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2707be1da707SZhi Wang R_VCS, D_ALL, 0, 12, NULL},
2708be1da707SZhi Wang
2709be1da707SZhi Wang {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2710be1da707SZhi Wang
2711be1da707SZhi Wang {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2712be1da707SZhi Wang 0, 12, NULL},
2713be1da707SZhi Wang
2714be1da707SZhi Wang {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
27153035e8cdSGao, Fred 0, 12, NULL},
2716be1da707SZhi Wang };
2717be1da707SZhi Wang
add_cmd_entry(struct intel_gvt * gvt,struct cmd_entry * e)2718be1da707SZhi Wang static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2719be1da707SZhi Wang {
2720be1da707SZhi Wang hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2721be1da707SZhi Wang }
2722be1da707SZhi Wang
2723be1da707SZhi Wang /* call the cmd handler, and advance ip */
cmd_parser_exec(struct parser_exec_state * s)2724be1da707SZhi Wang static int cmd_parser_exec(struct parser_exec_state *s)
2725be1da707SZhi Wang {
2726ffc19776SChangbin Du struct intel_vgpu *vgpu = s->vgpu;
2727b007065aSJani Nikula const struct cmd_info *info;
2728be1da707SZhi Wang u32 cmd;
2729be1da707SZhi Wang int ret = 0;
2730be1da707SZhi Wang
2731be1da707SZhi Wang cmd = cmd_val(s, 0);
2732be1da707SZhi Wang
2733db47685dSZhao Yan /* fastpath for MI_NOOP */
2734db47685dSZhao Yan if (cmd == MI_NOOP)
2735db47685dSZhao Yan info = &cmd_info[mi_noop_index];
2736db47685dSZhao Yan else
27378fde4107SChris Wilson info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2738db47685dSZhao Yan
2739be1da707SZhi Wang if (info == NULL) {
27408fde4107SChris Wilson gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
27418fde4107SChris Wilson cmd, get_opcode(cmd, s->engine),
27428fde4107SChris Wilson repr_addr_type(s->buf_addr_type),
27438fde4107SChris Wilson s->engine->name, s->workload);
27445c56883aSfred gao return -EBADRQC;
2745be1da707SZhi Wang }
2746be1da707SZhi Wang
2747be1da707SZhi Wang s->info = info;
2748be1da707SZhi Wang
27498fde4107SChris Wilson trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
275096bebe39SZhao Yan cmd_length(s), s->buf_type, s->buf_addr_type,
275196bebe39SZhao Yan s->workload, info->name);
2752be1da707SZhi Wang
27531e2adc0dSGao, Fred if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
27541e2adc0dSGao, Fred ret = gvt_check_valid_cmd_length(cmd_length(s),
27551e2adc0dSGao, Fred info->valid_len);
27561e2adc0dSGao, Fred if (ret)
27571e2adc0dSGao, Fred return ret;
27581e2adc0dSGao, Fred }
27591e2adc0dSGao, Fred
2760be1da707SZhi Wang if (info->handler) {
2761be1da707SZhi Wang ret = info->handler(s);
2762be1da707SZhi Wang if (ret < 0) {
2763695fbc08STina Zhang gvt_vgpu_err("%s handler error\n", info->name);
2764be1da707SZhi Wang return ret;
2765be1da707SZhi Wang }
2766be1da707SZhi Wang }
2767be1da707SZhi Wang
2768be1da707SZhi Wang if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2769be1da707SZhi Wang ret = cmd_advance_default(s);
2770be1da707SZhi Wang if (ret) {
2771695fbc08STina Zhang gvt_vgpu_err("%s IP advance error\n", info->name);
2772be1da707SZhi Wang return ret;
2773be1da707SZhi Wang }
2774be1da707SZhi Wang }
2775be1da707SZhi Wang return 0;
2776be1da707SZhi Wang }
2777be1da707SZhi Wang
gma_out_of_range(unsigned long gma,unsigned long gma_head,unsigned int gma_tail)2778be1da707SZhi Wang static inline bool gma_out_of_range(unsigned long gma,
2779be1da707SZhi Wang unsigned long gma_head, unsigned int gma_tail)
2780be1da707SZhi Wang {
2781be1da707SZhi Wang if (gma_tail >= gma_head)
2782be1da707SZhi Wang return (gma < gma_head) || (gma > gma_tail);
2783be1da707SZhi Wang else
2784be1da707SZhi Wang return (gma > gma_tail) && (gma < gma_head);
2785be1da707SZhi Wang }
2786be1da707SZhi Wang
27875c56883aSfred gao /* Keep the consistent return type, e.g EBADRQC for unknown
27885c56883aSfred gao * cmd, EFAULT for invalid address, EPERM for nonpriv. later
27895c56883aSfred gao * works as the input of VM healthy status.
27905c56883aSfred gao */
command_scan(struct parser_exec_state * s,unsigned long rb_head,unsigned long rb_tail,unsigned long rb_start,unsigned long rb_len)2791be1da707SZhi Wang static int command_scan(struct parser_exec_state *s,
2792be1da707SZhi Wang unsigned long rb_head, unsigned long rb_tail,
2793be1da707SZhi Wang unsigned long rb_start, unsigned long rb_len)
2794be1da707SZhi Wang {
2795be1da707SZhi Wang
2796be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_bottom;
2797be1da707SZhi Wang int ret = 0;
2798695fbc08STina Zhang struct intel_vgpu *vgpu = s->vgpu;
2799be1da707SZhi Wang
2800be1da707SZhi Wang gma_head = rb_start + rb_head;
2801be1da707SZhi Wang gma_tail = rb_start + rb_tail;
2802be1da707SZhi Wang gma_bottom = rb_start + rb_len;
2803be1da707SZhi Wang
2804be1da707SZhi Wang while (s->ip_gma != gma_tail) {
2805493f30cdSYan Zhao if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2806493f30cdSYan Zhao s->buf_type == RING_BUFFER_CTX) {
2807be1da707SZhi Wang if (!(s->ip_gma >= rb_start) ||
2808be1da707SZhi Wang !(s->ip_gma < gma_bottom)) {
2809695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of ring scope."
2810be1da707SZhi Wang "(base:0x%lx, bottom: 0x%lx)\n",
2811be1da707SZhi Wang s->ip_gma, rb_start,
2812be1da707SZhi Wang gma_bottom);
2813be1da707SZhi Wang parser_exec_state_dump(s);
28145c56883aSfred gao return -EFAULT;
2815be1da707SZhi Wang }
2816be1da707SZhi Wang if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2817695fbc08STina Zhang gvt_vgpu_err("ip_gma %lx out of range."
2818be1da707SZhi Wang "base 0x%lx head 0x%lx tail 0x%lx\n",
2819be1da707SZhi Wang s->ip_gma, rb_start,
2820be1da707SZhi Wang rb_head, rb_tail);
2821be1da707SZhi Wang parser_exec_state_dump(s);
2822be1da707SZhi Wang break;
2823be1da707SZhi Wang }
2824be1da707SZhi Wang }
2825be1da707SZhi Wang ret = cmd_parser_exec(s);
2826be1da707SZhi Wang if (ret) {
2827695fbc08STina Zhang gvt_vgpu_err("cmd parser error\n");
2828be1da707SZhi Wang parser_exec_state_dump(s);
2829be1da707SZhi Wang break;
2830be1da707SZhi Wang }
2831be1da707SZhi Wang }
2832be1da707SZhi Wang
2833be1da707SZhi Wang return ret;
2834be1da707SZhi Wang }
2835be1da707SZhi Wang
scan_workload(struct intel_vgpu_workload * workload)2836be1da707SZhi Wang static int scan_workload(struct intel_vgpu_workload *workload)
2837be1da707SZhi Wang {
2838f645d22bSZhi Wang unsigned long gma_head, gma_tail;
2839be1da707SZhi Wang struct parser_exec_state s;
2840be1da707SZhi Wang int ret = 0;
2841be1da707SZhi Wang
2842be1da707SZhi Wang /* ring base is page aligned */
28439556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2844be1da707SZhi Wang return -EINVAL;
2845be1da707SZhi Wang
2846be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head;
2847be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail;
2848be1da707SZhi Wang
2849be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION;
2850be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER;
2851be1da707SZhi Wang s.vgpu = workload->vgpu;
28528fde4107SChris Wilson s.engine = workload->engine;
2853be1da707SZhi Wang s.ring_start = workload->rb_start;
2854be1da707SZhi Wang s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2855be1da707SZhi Wang s.ring_head = gma_head;
2856be1da707SZhi Wang s.ring_tail = gma_tail;
2857be1da707SZhi Wang s.rb_va = workload->shadow_ring_buffer_va;
2858be1da707SZhi Wang s.workload = workload;
2859ef75c685Sfred gao s.is_ctx_wa = false;
2860be1da707SZhi Wang
28618fde4107SChris Wilson if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2862be1da707SZhi Wang return 0;
2863be1da707SZhi Wang
2864be1da707SZhi Wang ret = ip_gma_set(&s, gma_head);
2865be1da707SZhi Wang if (ret)
2866be1da707SZhi Wang goto out;
2867be1da707SZhi Wang
2868be1da707SZhi Wang ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2869be1da707SZhi Wang workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2870be1da707SZhi Wang
2871be1da707SZhi Wang out:
2872be1da707SZhi Wang return ret;
2873be1da707SZhi Wang }
2874be1da707SZhi Wang
scan_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)2875be1da707SZhi Wang static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2876be1da707SZhi Wang {
2877be1da707SZhi Wang
2878f645d22bSZhi Wang unsigned long gma_head, gma_tail, ring_size, ring_tail;
2879be1da707SZhi Wang struct parser_exec_state s;
2880be1da707SZhi Wang int ret = 0;
2881c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx,
2882c10c1255STina Zhang struct intel_vgpu_workload,
2883c10c1255STina Zhang wa_ctx);
2884be1da707SZhi Wang
2885be1da707SZhi Wang /* ring base is page aligned */
28869556e118SZhi Wang if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
28879556e118SZhi Wang I915_GTT_PAGE_SIZE)))
2888be1da707SZhi Wang return -EINVAL;
2889be1da707SZhi Wang
28902e679d48SJani Nikula ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2891be1da707SZhi Wang ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2892be1da707SZhi Wang PAGE_SIZE);
2893be1da707SZhi Wang gma_head = wa_ctx->indirect_ctx.guest_gma;
2894be1da707SZhi Wang gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2895be1da707SZhi Wang
2896be1da707SZhi Wang s.buf_type = RING_BUFFER_INSTRUCTION;
2897be1da707SZhi Wang s.buf_addr_type = GTT_BUFFER;
2898c10c1255STina Zhang s.vgpu = workload->vgpu;
28998fde4107SChris Wilson s.engine = workload->engine;
2900be1da707SZhi Wang s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2901be1da707SZhi Wang s.ring_size = ring_size;
2902be1da707SZhi Wang s.ring_head = gma_head;
2903be1da707SZhi Wang s.ring_tail = gma_tail;
2904be1da707SZhi Wang s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2905c10c1255STina Zhang s.workload = workload;
2906ef75c685Sfred gao s.is_ctx_wa = true;
2907be1da707SZhi Wang
2908be1da707SZhi Wang ret = ip_gma_set(&s, gma_head);
2909be1da707SZhi Wang if (ret)
2910be1da707SZhi Wang goto out;
2911be1da707SZhi Wang
2912be1da707SZhi Wang ret = command_scan(&s, 0, ring_tail,
2913be1da707SZhi Wang wa_ctx->indirect_ctx.guest_gma, ring_size);
2914be1da707SZhi Wang out:
2915be1da707SZhi Wang return ret;
2916be1da707SZhi Wang }
2917be1da707SZhi Wang
shadow_workload_ring_buffer(struct intel_vgpu_workload * workload)2918be1da707SZhi Wang static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2919be1da707SZhi Wang {
2920be1da707SZhi Wang struct intel_vgpu *vgpu = workload->vgpu;
2921325eb94aSZhi Wang struct intel_vgpu_submission *s = &vgpu->submission;
2922be1da707SZhi Wang unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
29230a53bc07Sfred gao void *shadow_ring_buffer_va;
2924be1da707SZhi Wang int ret;
2925be1da707SZhi Wang
2926be1da707SZhi Wang guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2927be1da707SZhi Wang
2928be1da707SZhi Wang /* calculate workload ring buffer size */
2929be1da707SZhi Wang workload->rb_len = (workload->rb_tail + guest_rb_size -
2930be1da707SZhi Wang workload->rb_head) % guest_rb_size;
2931be1da707SZhi Wang
2932be1da707SZhi Wang gma_head = workload->rb_start + workload->rb_head;
2933be1da707SZhi Wang gma_tail = workload->rb_start + workload->rb_tail;
2934be1da707SZhi Wang gma_top = workload->rb_start + guest_rb_size;
2935be1da707SZhi Wang
29368fde4107SChris Wilson if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
29378cf80a2eSZhi Wang void *p;
2938bf4097eaSZhi Wang
29390a53bc07Sfred gao /* realloc the new ring buffer if needed */
29408fde4107SChris Wilson p = krealloc(s->ring_scan_buffer[workload->engine->id],
29418fde4107SChris Wilson workload->rb_len, GFP_KERNEL);
2942bf4097eaSZhi Wang if (!p) {
29438cf80a2eSZhi Wang gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
29440a53bc07Sfred gao return -ENOMEM;
29450a53bc07Sfred gao }
29468fde4107SChris Wilson s->ring_scan_buffer[workload->engine->id] = p;
29478fde4107SChris Wilson s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
29480a53bc07Sfred gao }
29490a53bc07Sfred gao
29508fde4107SChris Wilson shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2951be1da707SZhi Wang
2952be1da707SZhi Wang /* get shadow ring buffer va */
29530a53bc07Sfred gao workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2954be1da707SZhi Wang
2955be1da707SZhi Wang /* head > tail --> copy head <-> top */
2956be1da707SZhi Wang if (gma_head > gma_tail) {
2957be1da707SZhi Wang ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
29580a53bc07Sfred gao gma_head, gma_top, shadow_ring_buffer_va);
29598bcad07aSZhenyu Wang if (ret < 0) {
2960695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n");
2961be1da707SZhi Wang return ret;
2962be1da707SZhi Wang }
29630a53bc07Sfred gao shadow_ring_buffer_va += ret;
2964be1da707SZhi Wang gma_head = workload->rb_start;
2965be1da707SZhi Wang }
2966be1da707SZhi Wang
2967be1da707SZhi Wang /* copy head or start <-> tail */
29680a53bc07Sfred gao ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
29690a53bc07Sfred gao shadow_ring_buffer_va);
29708bcad07aSZhenyu Wang if (ret < 0) {
2971695fbc08STina Zhang gvt_vgpu_err("fail to copy guest ring buffer\n");
2972be1da707SZhi Wang return ret;
2973be1da707SZhi Wang }
2974be1da707SZhi Wang return 0;
2975be1da707SZhi Wang }
2976be1da707SZhi Wang
intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload * workload)297789ea20b9SPing Gao int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2978be1da707SZhi Wang {
2979be1da707SZhi Wang int ret;
2980695fbc08STina Zhang struct intel_vgpu *vgpu = workload->vgpu;
2981be1da707SZhi Wang
2982be1da707SZhi Wang ret = shadow_workload_ring_buffer(workload);
2983be1da707SZhi Wang if (ret) {
2984695fbc08STina Zhang gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2985be1da707SZhi Wang return ret;
2986be1da707SZhi Wang }
2987be1da707SZhi Wang
2988be1da707SZhi Wang ret = scan_workload(workload);
2989be1da707SZhi Wang if (ret) {
2990695fbc08STina Zhang gvt_vgpu_err("scan workload error\n");
2991be1da707SZhi Wang return ret;
2992be1da707SZhi Wang }
2993be1da707SZhi Wang return 0;
2994be1da707SZhi Wang }
2995be1da707SZhi Wang
shadow_indirect_ctx(struct intel_shadow_wa_ctx * wa_ctx)2996be1da707SZhi Wang static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2997be1da707SZhi Wang {
2998be1da707SZhi Wang int ctx_size = wa_ctx->indirect_ctx.size;
2999be1da707SZhi Wang unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
3000c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx,
3001c10c1255STina Zhang struct intel_vgpu_workload,
3002c10c1255STina Zhang wa_ctx);
3003c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu;
3004894cf7d1SChris Wilson struct drm_i915_gem_object *obj;
3005be1da707SZhi Wang int ret = 0;
3006bcd0aedeSChris Wilson void *map;
3007be1da707SZhi Wang
30088fde4107SChris Wilson obj = i915_gem_object_create_shmem(workload->engine->i915,
3009894cf7d1SChris Wilson roundup(ctx_size + CACHELINE_BYTES,
3010894cf7d1SChris Wilson PAGE_SIZE));
3011894cf7d1SChris Wilson if (IS_ERR(obj))
3012894cf7d1SChris Wilson return PTR_ERR(obj);
3013be1da707SZhi Wang
3014be1da707SZhi Wang /* get the va of the shadow batch buffer */
3015bcd0aedeSChris Wilson map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3016bcd0aedeSChris Wilson if (IS_ERR(map)) {
3017695fbc08STina Zhang gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3018bcd0aedeSChris Wilson ret = PTR_ERR(map);
3019bcd0aedeSChris Wilson goto put_obj;
3020be1da707SZhi Wang }
3021be1da707SZhi Wang
302280f0b679SMaarten Lankhorst i915_gem_object_lock(obj, NULL);
3023894cf7d1SChris Wilson ret = i915_gem_object_set_to_cpu_domain(obj, false);
30246951e589SChris Wilson i915_gem_object_unlock(obj);
3025be1da707SZhi Wang if (ret) {
3026695fbc08STina Zhang gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3027be1da707SZhi Wang goto unmap_src;
3028be1da707SZhi Wang }
3029be1da707SZhi Wang
3030c10c1255STina Zhang ret = copy_gma_to_hva(workload->vgpu,
3031c10c1255STina Zhang workload->vgpu->gtt.ggtt_mm,
3032bcd0aedeSChris Wilson guest_gma, guest_gma + ctx_size,
3033bcd0aedeSChris Wilson map);
30348bcad07aSZhenyu Wang if (ret < 0) {
3035695fbc08STina Zhang gvt_vgpu_err("fail to copy guest indirect ctx\n");
3036894cf7d1SChris Wilson goto unmap_src;
3037be1da707SZhi Wang }
3038be1da707SZhi Wang
3039894cf7d1SChris Wilson wa_ctx->indirect_ctx.obj = obj;
3040bcd0aedeSChris Wilson wa_ctx->indirect_ctx.shadow_va = map;
3041be1da707SZhi Wang return 0;
3042be1da707SZhi Wang
3043be1da707SZhi Wang unmap_src:
3044bcd0aedeSChris Wilson i915_gem_object_unpin_map(obj);
3045894cf7d1SChris Wilson put_obj:
3046ffeaf9aaSfred gao i915_gem_object_put(obj);
3047be1da707SZhi Wang return ret;
3048be1da707SZhi Wang }
3049be1da707SZhi Wang
combine_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3050be1da707SZhi Wang static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3051be1da707SZhi Wang {
305265c02404SVille Syrjälä u32 per_ctx_start[CACHELINE_DWORDS] = {};
3053be1da707SZhi Wang unsigned char *bb_start_sva;
3054be1da707SZhi Wang
30558f63fc2bSZhenyu Wang if (!wa_ctx->per_ctx.valid)
30568f63fc2bSZhenyu Wang return 0;
30578f63fc2bSZhenyu Wang
3058be1da707SZhi Wang per_ctx_start[0] = 0x18800001;
3059be1da707SZhi Wang per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3060be1da707SZhi Wang
3061be1da707SZhi Wang bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3062be1da707SZhi Wang wa_ctx->indirect_ctx.size;
3063be1da707SZhi Wang
3064be1da707SZhi Wang memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3065be1da707SZhi Wang
3066be1da707SZhi Wang return 0;
3067be1da707SZhi Wang }
3068be1da707SZhi Wang
intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3069be1da707SZhi Wang int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3070be1da707SZhi Wang {
3071be1da707SZhi Wang int ret;
3072c10c1255STina Zhang struct intel_vgpu_workload *workload = container_of(wa_ctx,
3073c10c1255STina Zhang struct intel_vgpu_workload,
3074c10c1255STina Zhang wa_ctx);
3075c10c1255STina Zhang struct intel_vgpu *vgpu = workload->vgpu;
3076be1da707SZhi Wang
3077be1da707SZhi Wang if (wa_ctx->indirect_ctx.size == 0)
3078be1da707SZhi Wang return 0;
3079be1da707SZhi Wang
3080be1da707SZhi Wang ret = shadow_indirect_ctx(wa_ctx);
3081be1da707SZhi Wang if (ret) {
3082695fbc08STina Zhang gvt_vgpu_err("fail to shadow indirect ctx\n");
3083be1da707SZhi Wang return ret;
3084be1da707SZhi Wang }
3085be1da707SZhi Wang
3086be1da707SZhi Wang combine_wa_ctx(wa_ctx);
3087be1da707SZhi Wang
3088be1da707SZhi Wang ret = scan_wa_ctx(wa_ctx);
3089be1da707SZhi Wang if (ret) {
3090695fbc08STina Zhang gvt_vgpu_err("scan wa ctx error\n");
3091be1da707SZhi Wang return ret;
3092be1da707SZhi Wang }
3093be1da707SZhi Wang
3094be1da707SZhi Wang return 0;
3095be1da707SZhi Wang }
3096be1da707SZhi Wang
3097493f30cdSYan Zhao /* generate dummy contexts by sending empty requests to HW, and let
3098493f30cdSYan Zhao * the HW to fill Engine Contexts. This dummy contexts are used for
3099493f30cdSYan Zhao * initialization purpose (update reg whitelist), so referred to as
3100493f30cdSYan Zhao * init context here
3101493f30cdSYan Zhao */
intel_gvt_update_reg_whitelist(struct intel_vgpu * vgpu)3102493f30cdSYan Zhao void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3103493f30cdSYan Zhao {
310497ea6565SChris Wilson const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3105493f30cdSYan Zhao struct intel_gvt *gvt = vgpu->gvt;
3106493f30cdSYan Zhao struct intel_engine_cs *engine;
3107493f30cdSYan Zhao enum intel_engine_id id;
3108493f30cdSYan Zhao
3109493f30cdSYan Zhao if (gvt->is_reg_whitelist_updated)
3110493f30cdSYan Zhao return;
3111493f30cdSYan Zhao
3112493f30cdSYan Zhao /* scan init ctx to update cmd accessible list */
311397ea6565SChris Wilson for_each_engine(engine, gvt->gt, id) {
3114493f30cdSYan Zhao struct parser_exec_state s;
311597ea6565SChris Wilson void *vaddr;
311697ea6565SChris Wilson int ret;
3117493f30cdSYan Zhao
311897ea6565SChris Wilson if (!engine->default_state)
311997ea6565SChris Wilson continue;
3120493f30cdSYan Zhao
312197ea6565SChris Wilson vaddr = shmem_pin_map(engine->default_state);
3122e87197fbSDan Carpenter if (!vaddr) {
3123e87197fbSDan Carpenter gvt_err("failed to map %s->default state\n",
3124e87197fbSDan Carpenter engine->name);
312597ea6565SChris Wilson return;
3126493f30cdSYan Zhao }
3127493f30cdSYan Zhao
3128493f30cdSYan Zhao s.buf_type = RING_BUFFER_CTX;
3129493f30cdSYan Zhao s.buf_addr_type = GTT_BUFFER;
3130493f30cdSYan Zhao s.vgpu = vgpu;
3131493f30cdSYan Zhao s.engine = engine;
3132493f30cdSYan Zhao s.ring_start = 0;
313397ea6565SChris Wilson s.ring_size = engine->context_size - start;
3134493f30cdSYan Zhao s.ring_head = 0;
313597ea6565SChris Wilson s.ring_tail = s.ring_size;
3136493f30cdSYan Zhao s.rb_va = vaddr + start;
3137493f30cdSYan Zhao s.workload = NULL;
3138493f30cdSYan Zhao s.is_ctx_wa = false;
3139493f30cdSYan Zhao s.is_init_ctx = true;
3140493f30cdSYan Zhao
3141493f30cdSYan Zhao /* skipping the first RING_CTX_SIZE(0x50) dwords */
3142493f30cdSYan Zhao ret = ip_gma_set(&s, RING_CTX_SIZE);
314397ea6565SChris Wilson if (ret == 0) {
314497ea6565SChris Wilson ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3145493f30cdSYan Zhao if (ret)
3146493f30cdSYan Zhao gvt_err("Scan init ctx error\n");
3147493f30cdSYan Zhao }
3148493f30cdSYan Zhao
314997ea6565SChris Wilson shmem_unpin_map(engine->default_state, vaddr);
315097ea6565SChris Wilson if (ret)
315197ea6565SChris Wilson return;
315297ea6565SChris Wilson }
315397ea6565SChris Wilson
3154493f30cdSYan Zhao gvt->is_reg_whitelist_updated = true;
3155493f30cdSYan Zhao }
3156493f30cdSYan Zhao
intel_gvt_scan_engine_context(struct intel_vgpu_workload * workload)31573c4f2120SYan Zhao int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
31583c4f2120SYan Zhao {
31593c4f2120SYan Zhao struct intel_vgpu *vgpu = workload->vgpu;
31603c4f2120SYan Zhao unsigned long gma_head, gma_tail, gma_start, ctx_size;
31613c4f2120SYan Zhao struct parser_exec_state s;
31623c4f2120SYan Zhao int ring_id = workload->engine->id;
31633c4f2120SYan Zhao struct intel_context *ce = vgpu->submission.shadow[ring_id];
31643c4f2120SYan Zhao int ret;
31653c4f2120SYan Zhao
31663c4f2120SYan Zhao GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
31673c4f2120SYan Zhao
31683c4f2120SYan Zhao ctx_size = workload->engine->context_size - PAGE_SIZE;
31693c4f2120SYan Zhao
31703c4f2120SYan Zhao /* Only ring contxt is loaded to HW for inhibit context, no need to
31713c4f2120SYan Zhao * scan engine context
31723c4f2120SYan Zhao */
31733c4f2120SYan Zhao if (is_inhibit_context(ce))
31743c4f2120SYan Zhao return 0;
31753c4f2120SYan Zhao
31763c4f2120SYan Zhao gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
31773c4f2120SYan Zhao gma_head = 0;
31783c4f2120SYan Zhao gma_tail = ctx_size;
31793c4f2120SYan Zhao
31803c4f2120SYan Zhao s.buf_type = RING_BUFFER_CTX;
31813c4f2120SYan Zhao s.buf_addr_type = GTT_BUFFER;
31823c4f2120SYan Zhao s.vgpu = workload->vgpu;
31833c4f2120SYan Zhao s.engine = workload->engine;
31843c4f2120SYan Zhao s.ring_start = gma_start;
31853c4f2120SYan Zhao s.ring_size = ctx_size;
31863c4f2120SYan Zhao s.ring_head = gma_start + gma_head;
31873c4f2120SYan Zhao s.ring_tail = gma_start + gma_tail;
31883c4f2120SYan Zhao s.rb_va = ce->lrc_reg_state;
31893c4f2120SYan Zhao s.workload = workload;
31903c4f2120SYan Zhao s.is_ctx_wa = false;
31913c4f2120SYan Zhao s.is_init_ctx = false;
31923c4f2120SYan Zhao
31933c4f2120SYan Zhao /* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
31943c4f2120SYan Zhao * context
31953c4f2120SYan Zhao */
31963c4f2120SYan Zhao ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
31973c4f2120SYan Zhao if (ret)
31983c4f2120SYan Zhao goto out;
31993c4f2120SYan Zhao
32003c4f2120SYan Zhao ret = command_scan(&s, gma_head, gma_tail,
32013c4f2120SYan Zhao gma_start, ctx_size);
32023c4f2120SYan Zhao out:
32033c4f2120SYan Zhao if (ret)
32043c4f2120SYan Zhao gvt_vgpu_err("scan shadow ctx error\n");
32053c4f2120SYan Zhao
32063c4f2120SYan Zhao return ret;
32073c4f2120SYan Zhao }
32083c4f2120SYan Zhao
init_cmd_table(struct intel_gvt * gvt)3209be1da707SZhi Wang static int init_cmd_table(struct intel_gvt *gvt)
3210be1da707SZhi Wang {
32118fde4107SChris Wilson unsigned int gen_type = intel_gvt_get_device_type(gvt);
3212be1da707SZhi Wang int i;
3213be1da707SZhi Wang
3214be1da707SZhi Wang for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
32158fde4107SChris Wilson struct cmd_entry *e;
32168fde4107SChris Wilson
3217be1da707SZhi Wang if (!(cmd_info[i].devices & gen_type))
3218be1da707SZhi Wang continue;
3219be1da707SZhi Wang
3220be1da707SZhi Wang e = kzalloc(sizeof(*e), GFP_KERNEL);
3221be1da707SZhi Wang if (!e)
3222be1da707SZhi Wang return -ENOMEM;
3223be1da707SZhi Wang
3224be1da707SZhi Wang e->info = &cmd_info[i];
3225db47685dSZhao Yan if (cmd_info[i].opcode == OP_MI_NOOP)
3226db47685dSZhao Yan mi_noop_index = i;
3227be1da707SZhi Wang
3228be1da707SZhi Wang INIT_HLIST_NODE(&e->hlist);
3229be1da707SZhi Wang add_cmd_entry(gvt, e);
3230be1da707SZhi Wang gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3231be1da707SZhi Wang e->info->name, e->info->opcode, e->info->flag,
3232be1da707SZhi Wang e->info->devices, e->info->rings);
3233be1da707SZhi Wang }
32348fde4107SChris Wilson
3235be1da707SZhi Wang return 0;
3236be1da707SZhi Wang }
3237be1da707SZhi Wang
clean_cmd_table(struct intel_gvt * gvt)3238be1da707SZhi Wang static void clean_cmd_table(struct intel_gvt *gvt)
3239be1da707SZhi Wang {
3240be1da707SZhi Wang struct hlist_node *tmp;
3241be1da707SZhi Wang struct cmd_entry *e;
3242be1da707SZhi Wang int i;
3243be1da707SZhi Wang
3244be1da707SZhi Wang hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3245be1da707SZhi Wang kfree(e);
3246be1da707SZhi Wang
3247be1da707SZhi Wang hash_init(gvt->cmd_table);
3248be1da707SZhi Wang }
3249be1da707SZhi Wang
intel_gvt_clean_cmd_parser(struct intel_gvt * gvt)3250be1da707SZhi Wang void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3251be1da707SZhi Wang {
3252be1da707SZhi Wang clean_cmd_table(gvt);
3253be1da707SZhi Wang }
3254be1da707SZhi Wang
intel_gvt_init_cmd_parser(struct intel_gvt * gvt)3255be1da707SZhi Wang int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3256be1da707SZhi Wang {
3257be1da707SZhi Wang int ret;
3258be1da707SZhi Wang
3259be1da707SZhi Wang ret = init_cmd_table(gvt);
3260be1da707SZhi Wang if (ret) {
3261be1da707SZhi Wang intel_gvt_clean_cmd_parser(gvt);
3262be1da707SZhi Wang return ret;
3263be1da707SZhi Wang }
3264be1da707SZhi Wang return 0;
3265be1da707SZhi Wang }
3266