Lines Matching refs:vgpu
71 static void update_upstream_irq(struct intel_vgpu *vgpu,
183 * @vgpu: a vGPU
195 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
198 struct intel_gvt *gvt = vgpu->gvt;
202 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
203 (vgpu_vreg(vgpu, reg) ^ imr));
205 vgpu_vreg(vgpu, reg) = imr;
207 ops->check_pending_irq(vgpu);
214 * @vgpu: a vGPU
225 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
228 struct intel_gvt *gvt = vgpu->gvt;
231 u32 virtual_ier = vgpu_vreg(vgpu, reg);
233 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
243 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
244 vgpu_vreg(vgpu, reg) |= ier;
246 ops->check_pending_irq(vgpu);
253 * @vgpu: a vGPU
264 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
267 struct intel_gvt *gvt = vgpu->gvt;
273 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
274 (vgpu_vreg(vgpu, reg) ^ ier));
276 vgpu_vreg(vgpu, reg) = ier;
283 update_upstream_irq(vgpu, info);
285 ops->check_pending_irq(vgpu);
292 * @vgpu: a vGPU
303 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
306 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
307 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
311 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
312 (vgpu_vreg(vgpu, reg) ^ iir));
317 vgpu_vreg(vgpu, reg) &= ~iir;
320 update_upstream_irq(vgpu, info);
341 static void update_upstream_irq(struct intel_vgpu *vgpu,
344 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
345 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
351 u32 val = vgpu_vreg(vgpu,
353 & vgpu_vreg(vgpu,
383 vgpu_vreg(vgpu, isr) &= ~clear_bits;
384 vgpu_vreg(vgpu, isr) |= set_bits;
391 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
395 update_upstream_irq(vgpu, up_irq_info);
425 static void inject_virtual_interrupt(struct intel_vgpu *vgpu)
427 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;
431 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
432 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
433 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
442 trace_inject_msi(vgpu->id, addr, data);
445 * When guest is powered off, msi_trigger is set to NULL, but vgpu's
447 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe
448 * may be enabled, then once this vgpu is active, it will get inject
453 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
455 if (vgpu->msi_trigger)
456 eventfd_signal(vgpu->msi_trigger);
460 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
473 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
475 trace_propagate_event(vgpu->id, irq_name[event], bit);
476 set_bit(bit, (void *)&vgpu_vreg(vgpu,
483 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
485 if (!vgpu->irq.irq_warn_once[event]) {
486 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
487 vgpu->id, event, irq_name[event]);
488 vgpu->irq.irq_warn_once[event] = true;
490 propagate_event(irq, event, vgpu);
523 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
525 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
528 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
540 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
541 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
542 update_upstream_irq(vgpu, info);
545 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
547 inject_virtual_interrupt(vgpu);
669 * @vgpu: a vGPU
677 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
680 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
681 struct intel_gvt *gvt = vgpu->gvt;
689 handler(irq, event, vgpu);
691 ops->check_pending_irq(vgpu);