1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "i915_reg.h"
41 #include "gvt.h"
42 #include "i915_pvinfo.h"
43 #include "intel_mchbar_regs.h"
44 #include "display/bxt_dpio_phy_regs.h"
45 #include "display/i9xx_plane_regs.h"
46 #include "display/intel_cursor_regs.h"
47 #include "display/intel_display_types.h"
48 #include "display/intel_dmc_regs.h"
49 #include "display/intel_dp_aux_regs.h"
50 #include "display/intel_dpio_phy.h"
51 #include "display/intel_fbc.h"
52 #include "display/intel_fdi_regs.h"
53 #include "display/intel_pps_regs.h"
54 #include "display/intel_psr_regs.h"
55 #include "display/intel_sprite_regs.h"
56 #include "display/skl_universal_plane_regs.h"
57 #include "display/skl_watermark_regs.h"
58 #include "display/vlv_dsi_pll_regs.h"
59 #include "gt/intel_gt_regs.h"
60 #include <linux/vmalloc.h>
61
62 /* XXX FIXME i915 has changed PP_XXX definition */
63 #define PCH_PP_STATUS _MMIO(0xc7200)
64 #define PCH_PP_CONTROL _MMIO(0xc7204)
65 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
66 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
67 #define PCH_PP_DIVISOR _MMIO(0xc7210)
68
intel_gvt_get_device_type(struct intel_gvt * gvt)69 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
70 {
71 struct drm_i915_private *i915 = gvt->gt->i915;
72
73 if (IS_BROADWELL(i915))
74 return D_BDW;
75 else if (IS_SKYLAKE(i915))
76 return D_SKL;
77 else if (IS_KABYLAKE(i915))
78 return D_KBL;
79 else if (IS_BROXTON(i915))
80 return D_BXT;
81 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
82 return D_CFL;
83
84 return 0;
85 }
86
intel_gvt_match_device(struct intel_gvt * gvt,unsigned long device)87 static bool intel_gvt_match_device(struct intel_gvt *gvt,
88 unsigned long device)
89 {
90 return intel_gvt_get_device_type(gvt) & device;
91 }
92
read_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)93 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
94 void *p_data, unsigned int bytes)
95 {
96 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
97 }
98
write_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)99 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
100 void *p_data, unsigned int bytes)
101 {
102 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
103 }
104
intel_gvt_find_mmio_info(struct intel_gvt * gvt,unsigned int offset)105 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
106 unsigned int offset)
107 {
108 struct intel_gvt_mmio_info *e;
109
110 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
111 if (e->offset == offset)
112 return e;
113 }
114 return NULL;
115 }
116
setup_mmio_info(struct intel_gvt * gvt,u32 offset,u32 size,u16 flags,u32 addr_mask,u32 ro_mask,u32 device,gvt_mmio_func read,gvt_mmio_func write)117 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
118 u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
119 gvt_mmio_func read, gvt_mmio_func write)
120 {
121 struct intel_gvt_mmio_info *p;
122 u32 start, end, i;
123
124 if (!intel_gvt_match_device(gvt, device))
125 return 0;
126
127 if (WARN_ON(!IS_ALIGNED(offset, 4)))
128 return -EINVAL;
129
130 start = offset;
131 end = offset + size;
132
133 for (i = start; i < end; i += 4) {
134 p = intel_gvt_find_mmio_info(gvt, i);
135 if (!p) {
136 WARN(1, "assign a handler to a non-tracked mmio %x\n",
137 i);
138 return -ENODEV;
139 }
140 p->ro_mask = ro_mask;
141 gvt->mmio.mmio_attribute[i / 4] = flags;
142 if (read)
143 p->read = read;
144 if (write)
145 p->write = write;
146 }
147 return 0;
148 }
149
150 /**
151 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
152 * @gvt: a GVT device
153 * @offset: register offset
154 *
155 * Returns:
156 * The engine containing the offset within its mmio page.
157 */
158 const struct intel_engine_cs *
intel_gvt_render_mmio_to_engine(struct intel_gvt * gvt,unsigned int offset)159 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
160 {
161 struct intel_engine_cs *engine;
162 enum intel_engine_id id;
163
164 offset &= ~GENMASK(11, 0);
165 for_each_engine(engine, gvt->gt, id)
166 if (engine->mmio_base == offset)
167 return engine;
168
169 return NULL;
170 }
171
172 #define offset_to_fence_num(offset) \
173 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
174
175 #define fence_num_to_offset(num) \
176 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
177
178
enter_failsafe_mode(struct intel_vgpu * vgpu,int reason)179 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
180 {
181 switch (reason) {
182 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
183 pr_err("Detected your guest driver doesn't support GVT-g.\n");
184 break;
185 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
186 pr_err("Graphics resource is not enough for the guest\n");
187 break;
188 case GVT_FAILSAFE_GUEST_ERR:
189 pr_err("GVT Internal error for the guest\n");
190 break;
191 default:
192 break;
193 }
194 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
195 vgpu->failsafe = true;
196 }
197
sanitize_fence_mmio_access(struct intel_vgpu * vgpu,unsigned int fence_num,void * p_data,unsigned int bytes)198 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
199 unsigned int fence_num, void *p_data, unsigned int bytes)
200 {
201 unsigned int max_fence = vgpu_fence_sz(vgpu);
202
203 if (fence_num >= max_fence) {
204 gvt_vgpu_err("access oob fence reg %d/%d\n",
205 fence_num, max_fence);
206
207 /* When guest access oob fence regs without access
208 * pv_info first, we treat guest not supporting GVT,
209 * and we will let vgpu enter failsafe mode.
210 */
211 if (!vgpu->pv_notified)
212 enter_failsafe_mode(vgpu,
213 GVT_FAILSAFE_UNSUPPORTED_GUEST);
214
215 memset(p_data, 0, bytes);
216 return -EINVAL;
217 }
218 return 0;
219 }
220
gamw_echo_dev_rw_ia_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)221 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
222 unsigned int offset, void *p_data, unsigned int bytes)
223 {
224 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
225
226 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {
227 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
228 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
229 else if (!ips)
230 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
231 else {
232 /* All engines must be enabled together for vGPU,
233 * since we don't know which engine the ppgtt will
234 * bind to when shadowing.
235 */
236 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
237 ips);
238 return -EINVAL;
239 }
240 }
241
242 write_vreg(vgpu, offset, p_data, bytes);
243 return 0;
244 }
245
fence_mmio_read(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)246 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
247 void *p_data, unsigned int bytes)
248 {
249 int ret;
250
251 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
252 p_data, bytes);
253 if (ret)
254 return ret;
255 read_vreg(vgpu, off, p_data, bytes);
256 return 0;
257 }
258
fence_mmio_write(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)259 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
260 void *p_data, unsigned int bytes)
261 {
262 struct intel_gvt *gvt = vgpu->gvt;
263 unsigned int fence_num = offset_to_fence_num(off);
264 int ret;
265
266 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
267 if (ret)
268 return ret;
269 write_vreg(vgpu, off, p_data, bytes);
270
271 mmio_hw_access_pre(gvt->gt);
272 intel_vgpu_write_fence(vgpu, fence_num,
273 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
274 mmio_hw_access_post(gvt->gt);
275 return 0;
276 }
277
278 #define CALC_MODE_MASK_REG(old, new) \
279 (((new) & GENMASK(31, 16)) \
280 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
281 | ((new) & ((new) >> 16))))
282
mul_force_wake_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)283 static int mul_force_wake_write(struct intel_vgpu *vgpu,
284 unsigned int offset, void *p_data, unsigned int bytes)
285 {
286 u32 old, new;
287 u32 ack_reg_offset;
288
289 old = vgpu_vreg(vgpu, offset);
290 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
291
292 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) {
293 switch (offset) {
294 case FORCEWAKE_RENDER_GEN9_REG:
295 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
296 break;
297 case FORCEWAKE_GT_GEN9_REG:
298 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
299 break;
300 case FORCEWAKE_MEDIA_GEN9_REG:
301 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
302 break;
303 default:
304 /*should not hit here*/
305 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
306 return -EINVAL;
307 }
308 } else {
309 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
310 }
311
312 vgpu_vreg(vgpu, offset) = new;
313 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
314 return 0;
315 }
316
gdrst_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)317 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
318 void *p_data, unsigned int bytes)
319 {
320 intel_engine_mask_t engine_mask = 0;
321 u32 data;
322
323 write_vreg(vgpu, offset, p_data, bytes);
324 data = vgpu_vreg(vgpu, offset);
325
326 if (data & GEN6_GRDOM_FULL) {
327 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
328 engine_mask = ALL_ENGINES;
329 } else {
330 if (data & GEN6_GRDOM_RENDER) {
331 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
332 engine_mask |= BIT(RCS0);
333 }
334 if (data & GEN6_GRDOM_MEDIA) {
335 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
336 engine_mask |= BIT(VCS0);
337 }
338 if (data & GEN6_GRDOM_BLT) {
339 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
340 engine_mask |= BIT(BCS0);
341 }
342 if (data & GEN6_GRDOM_VECS) {
343 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
344 engine_mask |= BIT(VECS0);
345 }
346 if (data & GEN8_GRDOM_MEDIA2) {
347 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
348 engine_mask |= BIT(VCS1);
349 }
350 if (data & GEN9_GRDOM_GUC) {
351 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
352 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
353 }
354 engine_mask &= vgpu->gvt->gt->info.engine_mask;
355 }
356
357 /* vgpu_lock already hold by emulate mmio r/w */
358 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
359
360 /* sw will wait for the device to ack the reset request */
361 vgpu_vreg(vgpu, offset) = 0;
362
363 return 0;
364 }
365
gmbus_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)366 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
367 void *p_data, unsigned int bytes)
368 {
369 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
370 }
371
gmbus_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)372 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
373 void *p_data, unsigned int bytes)
374 {
375 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
376 }
377
pch_pp_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)378 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
379 unsigned int offset, void *p_data, unsigned int bytes)
380 {
381 write_vreg(vgpu, offset, p_data, bytes);
382
383 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
385 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
388
389 } else
390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
391 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
392 | PP_CYCLE_DELAY_ACTIVE);
393 return 0;
394 }
395
transconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)396 static int transconf_mmio_write(struct intel_vgpu *vgpu,
397 unsigned int offset, void *p_data, unsigned int bytes)
398 {
399 write_vreg(vgpu, offset, p_data, bytes);
400
401 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
402 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
403 else
404 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
405 return 0;
406 }
407
lcpll_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)408 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
409 void *p_data, unsigned int bytes)
410 {
411 write_vreg(vgpu, offset, p_data, bytes);
412
413 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
414 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
415 else
416 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
417
418 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
419 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
420 else
421 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
422
423 return 0;
424 }
425
dpy_reg_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)426 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
427 void *p_data, unsigned int bytes)
428 {
429 switch (offset) {
430 case 0xe651c:
431 case 0xe661c:
432 case 0xe671c:
433 case 0xe681c:
434 vgpu_vreg(vgpu, offset) = 1 << 17;
435 break;
436 case 0xe6c04:
437 vgpu_vreg(vgpu, offset) = 0x3;
438 break;
439 case 0xe6e1c:
440 vgpu_vreg(vgpu, offset) = 0x2f << 16;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 read_vreg(vgpu, offset, p_data, bytes);
447 return 0;
448 }
449
450 /*
451 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
452 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on
453 * setup_virtual_dp_monitor().
454 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled
455 * DPLL. Later guest driver may setup a different DPLLx when setting mode.
456 * So the correct sequence to find DP stream clock is:
457 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x.
458 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate.
459 * Then Refresh rate then can be calculated based on follow equations:
460 * Pixel clock = h_total * v_total * refresh_rate
461 * stream clock = Pixel clock
462 * ls_clk = DP bitrate
463 * Link M/N = strm_clk / ls_clk
464 */
465
bdw_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)466 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
467 {
468 u32 dp_br = 0;
469 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
470
471 switch (ddi_pll_sel) {
472 case PORT_CLK_SEL_LCPLL_2700:
473 dp_br = 270000 * 2;
474 break;
475 case PORT_CLK_SEL_LCPLL_1350:
476 dp_br = 135000 * 2;
477 break;
478 case PORT_CLK_SEL_LCPLL_810:
479 dp_br = 81000 * 2;
480 break;
481 case PORT_CLK_SEL_SPLL:
482 {
483 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
484 case SPLL_FREQ_810MHz:
485 dp_br = 81000 * 2;
486 break;
487 case SPLL_FREQ_1350MHz:
488 dp_br = 135000 * 2;
489 break;
490 case SPLL_FREQ_2700MHz:
491 dp_br = 270000 * 2;
492 break;
493 default:
494 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
495 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
496 break;
497 }
498 break;
499 }
500 case PORT_CLK_SEL_WRPLL1:
501 case PORT_CLK_SEL_WRPLL2:
502 {
503 u32 wrpll_ctl;
504 int refclk, n, p, r;
505
506 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1)
507 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
508 else
509 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
510
511 switch (wrpll_ctl & WRPLL_REF_MASK) {
512 case WRPLL_REF_PCH_SSC:
513 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
514 break;
515 case WRPLL_REF_LCPLL:
516 refclk = 2700000;
517 break;
518 default:
519 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
520 vgpu->id, port_name(port), wrpll_ctl);
521 goto out;
522 }
523
524 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK;
525 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
526 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
527
528 dp_br = (refclk * n / 10) / (p * r) * 2;
529 break;
530 }
531 default:
532 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
533 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
534 break;
535 }
536
537 out:
538 return dp_br;
539 }
540
bxt_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)541 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
542 {
543 u32 dp_br = 0;
544 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
545 enum dpio_phy phy = DPIO_PHY0;
546 enum dpio_channel ch = DPIO_CH0;
547 struct dpll clock = {};
548 u32 temp;
549
550 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */
551 switch (port) {
552 case PORT_A:
553 phy = DPIO_PHY1;
554 ch = DPIO_CH0;
555 break;
556 case PORT_B:
557 phy = DPIO_PHY0;
558 ch = DPIO_CH0;
559 break;
560 case PORT_C:
561 phy = DPIO_PHY0;
562 ch = DPIO_CH1;
563 break;
564 default:
565 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port));
566 goto out;
567 }
568
569 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
570 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) {
571 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n",
572 vgpu->id, port_name(port), temp);
573 goto out;
574 }
575
576 clock.m1 = 2;
577 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
578 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
579 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
580 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
581 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
582 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
583 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
584 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
585 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
586 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
587 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
588 clock.m = clock.m1 * clock.m2;
589 clock.p = clock.p1 * clock.p2 * 5;
590
591 if (clock.n == 0 || clock.p == 0) {
592 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
593 goto out;
594 }
595
596 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
597 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
598
599 dp_br = clock.dot;
600
601 out:
602 return dp_br;
603 }
604
skl_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)605 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
606 {
607 u32 dp_br = 0;
608 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0;
609
610 /* Find the enabled DPLL for the DDI/PORT */
611 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&
612 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {
613 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &
614 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
615 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
616 } else {
617 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n",
618 vgpu->id, port_name(port));
619 return dp_br;
620 }
621
622 /* Find PLL output frequency from correct DPLL, and get bir rate */
623 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &
624 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >>
625 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) {
626 case DPLL_CTRL1_LINK_RATE_810:
627 dp_br = 81000 * 2;
628 break;
629 case DPLL_CTRL1_LINK_RATE_1080:
630 dp_br = 108000 * 2;
631 break;
632 case DPLL_CTRL1_LINK_RATE_1350:
633 dp_br = 135000 * 2;
634 break;
635 case DPLL_CTRL1_LINK_RATE_1620:
636 dp_br = 162000 * 2;
637 break;
638 case DPLL_CTRL1_LINK_RATE_2160:
639 dp_br = 216000 * 2;
640 break;
641 case DPLL_CTRL1_LINK_RATE_2700:
642 dp_br = 270000 * 2;
643 break;
644 default:
645 dp_br = 0;
646 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n",
647 vgpu->id, port_name(port), dpll_id);
648 }
649
650 return dp_br;
651 }
652
vgpu_update_refresh_rate(struct intel_vgpu * vgpu)653 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
654 {
655 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
656 enum port port;
657 u32 dp_br, link_m, link_n, htotal, vtotal;
658
659 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
660 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &
661 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
662 if (port != PORT_B && port != PORT_D) {
663 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
664 return;
665 }
666
667 /* Calculate DP bitrate from PLL */
668 if (IS_BROADWELL(dev_priv))
669 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port);
670 else if (IS_BROXTON(dev_priv))
671 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port);
672 else
673 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
674
675 /* Get DP link symbol clock M/N */
676 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
677 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
678
679 /* Get H/V total from transcoder timing */
680 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
681 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
682
683 if (dp_br && link_n && htotal && vtotal) {
684 u64 pixel_clk = 0;
685 u32 new_rate = 0;
686 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
687
688 /* Calcuate pixel clock by (ls_clk * M / N) */
689 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
690 pixel_clk *= MSEC_PER_SEC;
691
692 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */
693 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
694
695 if (*old_rate != new_rate)
696 *old_rate = new_rate;
697
698 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n",
699 vgpu->id, pipe_name(PIPE_A), new_rate);
700 }
701 }
702
pipeconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)703 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
704 void *p_data, unsigned int bytes)
705 {
706 u32 data;
707
708 write_vreg(vgpu, offset, p_data, bytes);
709 data = vgpu_vreg(vgpu, offset);
710
711 if (data & TRANSCONF_ENABLE) {
712 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
713 vgpu_update_refresh_rate(vgpu);
714 vgpu_update_vblank_emulation(vgpu, true);
715 } else {
716 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
717 vgpu_update_vblank_emulation(vgpu, false);
718 }
719 return 0;
720 }
721
722 /* sorted in ascending order */
723 static i915_reg_t force_nonpriv_white_list[] = {
724 _MMIO(0xd80),
725 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
726 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
727 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
728 PS_INVOCATION_COUNT, //_MMIO(0x2348)
729 PS_DEPTH_COUNT, //_MMIO(0x2350)
730 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
731 _MMIO(0x2690),
732 _MMIO(0x2694),
733 _MMIO(0x2698),
734 _MMIO(0x2754),
735 _MMIO(0x28a0),
736 _MMIO(0x4de0),
737 _MMIO(0x4de4),
738 _MMIO(0x4dfc),
739 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
740 _MMIO(0x7014),
741 HDC_CHICKEN0,//_MMIO(0x7300)
742 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
743 _MMIO(0x7700),
744 _MMIO(0x7704),
745 _MMIO(0x7708),
746 _MMIO(0x770c),
747 _MMIO(0x83a8),
748 _MMIO(0xb110),
749 _MMIO(0xb118),
750 _MMIO(0xe100),
751 _MMIO(0xe18c),
752 _MMIO(0xe48c),
753 _MMIO(0xe5f4),
754 _MMIO(0x64844),
755 };
756
757 /* a simple bsearch */
in_whitelist(u32 reg)758 static inline bool in_whitelist(u32 reg)
759 {
760 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
761 i915_reg_t *array = force_nonpriv_white_list;
762
763 while (left < right) {
764 int mid = (left + right)/2;
765
766 if (reg > array[mid].reg)
767 left = mid + 1;
768 else if (reg < array[mid].reg)
769 right = mid;
770 else
771 return true;
772 }
773 return false;
774 }
775
force_nonpriv_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)776 static int force_nonpriv_write(struct intel_vgpu *vgpu,
777 unsigned int offset, void *p_data, unsigned int bytes)
778 {
779 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
780 const struct intel_engine_cs *engine =
781 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
782
783 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
784 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
785 vgpu->id, offset, bytes);
786 return -EINVAL;
787 }
788
789 if (!in_whitelist(reg_nonpriv) &&
790 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
791 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
792 vgpu->id, reg_nonpriv, offset);
793 } else
794 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
795
796 return 0;
797 }
798
ddi_buf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)799 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
800 void *p_data, unsigned int bytes)
801 {
802 write_vreg(vgpu, offset, p_data, bytes);
803
804 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
805 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
806 } else {
807 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
808 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
809 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
810 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
811 }
812 return 0;
813 }
814
fdi_rx_iir_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)815 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
816 unsigned int offset, void *p_data, unsigned int bytes)
817 {
818 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
819 return 0;
820 }
821
822 #define FDI_LINK_TRAIN_PATTERN1 0
823 #define FDI_LINK_TRAIN_PATTERN2 1
824
fdi_auto_training_started(struct intel_vgpu * vgpu)825 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
826 {
827 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
828 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
829 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
830
831 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
832 (rx_ctl & FDI_RX_ENABLE) &&
833 (rx_ctl & FDI_AUTO_TRAINING) &&
834 (tx_ctl & DP_TP_CTL_ENABLE) &&
835 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
836 return 1;
837 else
838 return 0;
839 }
840
check_fdi_rx_train_status(struct intel_vgpu * vgpu,enum pipe pipe,unsigned int train_pattern)841 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
842 enum pipe pipe, unsigned int train_pattern)
843 {
844 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
845 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
846 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
847 unsigned int fdi_iir_check_bits;
848
849 fdi_rx_imr = FDI_RX_IMR(pipe);
850 fdi_tx_ctl = FDI_TX_CTL(pipe);
851 fdi_rx_ctl = FDI_RX_CTL(pipe);
852
853 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
854 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
855 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
856 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
857 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
858 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
859 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
860 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
861 } else {
862 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
863 return -EINVAL;
864 }
865
866 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
867 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
868
869 /* If imr bit has been masked */
870 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
871 return 0;
872
873 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
874 == fdi_tx_check_bits)
875 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
876 == fdi_rx_check_bits))
877 return 1;
878 else
879 return 0;
880 }
881
882 #define INVALID_INDEX (~0U)
883
calc_index(unsigned int offset,i915_reg_t _start,i915_reg_t _next,i915_reg_t _end)884 static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
885 i915_reg_t _next, i915_reg_t _end)
886 {
887 u32 start = i915_mmio_reg_offset(_start);
888 u32 next = i915_mmio_reg_offset(_next);
889 u32 end = i915_mmio_reg_offset(_end);
890 u32 stride = next - start;
891
892 if (offset < start || offset > end)
893 return INVALID_INDEX;
894 offset -= start;
895 return offset / stride;
896 }
897
898 #define FDI_RX_CTL_TO_PIPE(offset) \
899 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
900
901 #define FDI_TX_CTL_TO_PIPE(offset) \
902 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
903
904 #define FDI_RX_IMR_TO_PIPE(offset) \
905 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
906
update_fdi_rx_iir_status(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)907 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
908 unsigned int offset, void *p_data, unsigned int bytes)
909 {
910 i915_reg_t fdi_rx_iir;
911 unsigned int index;
912 int ret;
913
914 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
915 index = FDI_RX_CTL_TO_PIPE(offset);
916 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
917 index = FDI_TX_CTL_TO_PIPE(offset);
918 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
919 index = FDI_RX_IMR_TO_PIPE(offset);
920 else {
921 gvt_vgpu_err("Unsupported registers %x\n", offset);
922 return -EINVAL;
923 }
924
925 write_vreg(vgpu, offset, p_data, bytes);
926
927 fdi_rx_iir = FDI_RX_IIR(index);
928
929 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
930 if (ret < 0)
931 return ret;
932 if (ret)
933 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
934
935 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
936 if (ret < 0)
937 return ret;
938 if (ret)
939 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
940
941 if (offset == _FDI_RXA_CTL)
942 if (fdi_auto_training_started(vgpu))
943 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
944 DP_TP_STATUS_AUTOTRAIN_DONE;
945 return 0;
946 }
947
948 #define DP_TP_CTL_TO_PORT(offset) \
949 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
950
dp_tp_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)951 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
952 void *p_data, unsigned int bytes)
953 {
954 i915_reg_t status_reg;
955 unsigned int index;
956 u32 data;
957
958 write_vreg(vgpu, offset, p_data, bytes);
959
960 index = DP_TP_CTL_TO_PORT(offset);
961 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
962 if (data == 0x2) {
963 status_reg = DP_TP_STATUS(index);
964 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
965 }
966 return 0;
967 }
968
dp_tp_status_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)969 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
970 unsigned int offset, void *p_data, unsigned int bytes)
971 {
972 u32 reg_val;
973 u32 sticky_mask;
974
975 reg_val = *((u32 *)p_data);
976 sticky_mask = GENMASK(27, 26) | (1 << 24);
977
978 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
979 (vgpu_vreg(vgpu, offset) & sticky_mask);
980 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
981 return 0;
982 }
983
pch_adpa_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)984 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
985 unsigned int offset, void *p_data, unsigned int bytes)
986 {
987 u32 data;
988
989 write_vreg(vgpu, offset, p_data, bytes);
990 data = vgpu_vreg(vgpu, offset);
991
992 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
993 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
994 return 0;
995 }
996
south_chicken2_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)997 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
998 unsigned int offset, void *p_data, unsigned int bytes)
999 {
1000 u32 data;
1001
1002 write_vreg(vgpu, offset, p_data, bytes);
1003 data = vgpu_vreg(vgpu, offset);
1004
1005 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
1006 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
1007 else
1008 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
1009 return 0;
1010 }
1011
1012 #define DSPSURF_TO_PIPE(dev_priv, offset) \
1013 calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
1014
pri_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1015 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1016 void *p_data, unsigned int bytes)
1017 {
1018 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1019 u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset);
1020 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1021
1022 write_vreg(vgpu, offset, p_data, bytes);
1023 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1024
1025 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1026
1027 if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP)
1028 intel_vgpu_trigger_virtual_event(vgpu, event);
1029 else
1030 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1031
1032 return 0;
1033 }
1034
1035 #define SPRSURF_TO_PIPE(offset) \
1036 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
1037
spr_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1038 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1039 void *p_data, unsigned int bytes)
1040 {
1041 u32 pipe = SPRSURF_TO_PIPE(offset);
1042 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
1043
1044 write_vreg(vgpu, offset, p_data, bytes);
1045 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1046
1047 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
1048 intel_vgpu_trigger_virtual_event(vgpu, event);
1049 else
1050 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1051
1052 return 0;
1053 }
1054
reg50080_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1055 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
1056 unsigned int offset, void *p_data,
1057 unsigned int bytes)
1058 {
1059 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1060 enum pipe pipe = REG_50080_TO_PIPE(offset);
1061 enum plane_id plane = REG_50080_TO_PLANE(offset);
1062 int event = SKL_FLIP_EVENT(pipe, plane);
1063
1064 write_vreg(vgpu, offset, p_data, bytes);
1065 if (plane == PLANE_PRIMARY) {
1066 vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1067 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1068 } else {
1069 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1070 }
1071
1072 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
1073 intel_vgpu_trigger_virtual_event(vgpu, event);
1074 else
1075 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1076
1077 return 0;
1078 }
1079
trigger_aux_channel_interrupt(struct intel_vgpu * vgpu,unsigned int reg)1080 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
1081 unsigned int reg)
1082 {
1083 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1084 enum intel_gvt_event_type event;
1085
1086 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
1087 event = AUX_CHANNEL_A;
1088 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
1089 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
1090 event = AUX_CHANNEL_B;
1091 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
1092 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
1093 event = AUX_CHANNEL_C;
1094 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
1095 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
1096 event = AUX_CHANNEL_D;
1097 else {
1098 drm_WARN_ON(&dev_priv->drm, true);
1099 return -EINVAL;
1100 }
1101
1102 intel_vgpu_trigger_virtual_event(vgpu, event);
1103 return 0;
1104 }
1105
dp_aux_ch_ctl_trans_done(struct intel_vgpu * vgpu,u32 value,unsigned int reg,int len,bool data_valid)1106 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
1107 unsigned int reg, int len, bool data_valid)
1108 {
1109 /* mark transaction done */
1110 value |= DP_AUX_CH_CTL_DONE;
1111 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
1112 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
1113
1114 if (data_valid)
1115 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
1116 else
1117 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
1118
1119 /* message size */
1120 value &= ~(0xf << 20);
1121 value |= (len << 20);
1122 vgpu_vreg(vgpu, reg) = value;
1123
1124 if (value & DP_AUX_CH_CTL_INTERRUPT)
1125 return trigger_aux_channel_interrupt(vgpu, reg);
1126 return 0;
1127 }
1128
dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data * dpcd,u8 t)1129 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
1130 u8 t)
1131 {
1132 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
1133 /* training pattern 1 for CR */
1134 /* set LANE0_CR_DONE, LANE1_CR_DONE */
1135 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
1136 /* set LANE2_CR_DONE, LANE3_CR_DONE */
1137 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
1138 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
1139 DPCD_TRAINING_PATTERN_2) {
1140 /* training pattern 2 for EQ */
1141 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
1142 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
1143 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
1144 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
1145 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
1146 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
1147 /* set INTERLANE_ALIGN_DONE */
1148 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
1149 DPCD_INTERLANE_ALIGN_DONE;
1150 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
1151 DPCD_LINK_TRAINING_DISABLED) {
1152 /* finish link training */
1153 /* set sink status as synchronized */
1154 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
1155 }
1156 }
1157
1158 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1159
1160 #define dpy_is_valid_port(port) \
1161 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
1162
dp_aux_ch_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1163 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
1164 unsigned int offset, void *p_data, unsigned int bytes)
1165 {
1166 struct intel_vgpu_display *display = &vgpu->display;
1167 int msg, addr, ctrl, op, len;
1168 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
1169 struct intel_vgpu_dpcd_data *dpcd = NULL;
1170 struct intel_vgpu_port *port = NULL;
1171 u32 data;
1172
1173 if (!dpy_is_valid_port(port_index)) {
1174 gvt_vgpu_err("Unsupported DP port access!\n");
1175 return 0;
1176 }
1177
1178 write_vreg(vgpu, offset, p_data, bytes);
1179 data = vgpu_vreg(vgpu, offset);
1180
1181 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 &&
1182 offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {
1183 /* SKL DPB/C/D aux ctl register changed */
1184 return 0;
1185 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
1186 offset != i915_mmio_reg_offset(port_index ?
1187 PCH_DP_AUX_CH_CTL(port_index) :
1188 DP_AUX_CH_CTL(port_index))) {
1189 /* write to the data registers */
1190 return 0;
1191 }
1192
1193 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
1194 /* just want to clear the sticky bits */
1195 vgpu_vreg(vgpu, offset) = 0;
1196 return 0;
1197 }
1198
1199 port = &display->ports[port_index];
1200 dpcd = port->dpcd;
1201
1202 /* read out message from DATA1 register */
1203 msg = vgpu_vreg(vgpu, offset + 4);
1204 addr = (msg >> 8) & 0xffff;
1205 ctrl = (msg >> 24) & 0xff;
1206 len = msg & 0xff;
1207 op = ctrl >> 4;
1208
1209 if (op == GVT_AUX_NATIVE_WRITE) {
1210 int t;
1211 u8 buf[16];
1212
1213 if ((addr + len + 1) >= DPCD_SIZE) {
1214 /*
1215 * Write request exceeds what we supported,
1216 * DCPD spec: When a Source Device is writing a DPCD
1217 * address not supported by the Sink Device, the Sink
1218 * Device shall reply with AUX NACK and “M” equal to
1219 * zero.
1220 */
1221
1222 /* NAK the write */
1223 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
1224 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
1225 return 0;
1226 }
1227
1228 /*
1229 * Write request format: Headr (command + address + size) occupies
1230 * 4 bytes, followed by (len + 1) bytes of data. See details at
1231 * intel_dp_aux_transfer().
1232 */
1233 if ((len + 1 + 4) > AUX_BURST_SIZE) {
1234 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1235 return -EINVAL;
1236 }
1237
1238 /* unpack data from vreg to buf */
1239 for (t = 0; t < 4; t++) {
1240 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
1241
1242 buf[t * 4] = (r >> 24) & 0xff;
1243 buf[t * 4 + 1] = (r >> 16) & 0xff;
1244 buf[t * 4 + 2] = (r >> 8) & 0xff;
1245 buf[t * 4 + 3] = r & 0xff;
1246 }
1247
1248 /* write to virtual DPCD */
1249 if (dpcd && dpcd->data_valid) {
1250 for (t = 0; t <= len; t++) {
1251 int p = addr + t;
1252
1253 dpcd->data[p] = buf[t];
1254 /* check for link training */
1255 if (p == DPCD_TRAINING_PATTERN_SET)
1256 dp_aux_ch_ctl_link_training(dpcd,
1257 buf[t]);
1258 }
1259 }
1260
1261 /* ACK the write */
1262 vgpu_vreg(vgpu, offset + 4) = 0;
1263 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1264 dpcd && dpcd->data_valid);
1265 return 0;
1266 }
1267
1268 if (op == GVT_AUX_NATIVE_READ) {
1269 int idx, i, ret = 0;
1270
1271 if ((addr + len + 1) >= DPCD_SIZE) {
1272 /*
1273 * read request exceeds what we supported
1274 * DPCD spec: A Sink Device receiving a Native AUX CH
1275 * read request for an unsupported DPCD address must
1276 * reply with an AUX ACK and read data set equal to
1277 * zero instead of replying with AUX NACK.
1278 */
1279
1280 /* ACK the READ*/
1281 vgpu_vreg(vgpu, offset + 4) = 0;
1282 vgpu_vreg(vgpu, offset + 8) = 0;
1283 vgpu_vreg(vgpu, offset + 12) = 0;
1284 vgpu_vreg(vgpu, offset + 16) = 0;
1285 vgpu_vreg(vgpu, offset + 20) = 0;
1286
1287 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1288 true);
1289 return 0;
1290 }
1291
1292 for (idx = 1; idx <= 5; idx++) {
1293 /* clear the data registers */
1294 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1295 }
1296
1297 /*
1298 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1299 */
1300 if ((len + 2) > AUX_BURST_SIZE) {
1301 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1302 return -EINVAL;
1303 }
1304
1305 /* read from virtual DPCD to vreg */
1306 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1307 if (dpcd && dpcd->data_valid) {
1308 for (i = 1; i <= (len + 1); i++) {
1309 int t;
1310
1311 t = dpcd->data[addr + i - 1];
1312 t <<= (24 - 8 * (i % 4));
1313 ret |= t;
1314
1315 if ((i % 4 == 3) || (i == (len + 1))) {
1316 vgpu_vreg(vgpu, offset +
1317 (i / 4 + 1) * 4) = ret;
1318 ret = 0;
1319 }
1320 }
1321 }
1322 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1323 dpcd && dpcd->data_valid);
1324 return 0;
1325 }
1326
1327 /* i2c transaction starts */
1328 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1329
1330 if (data & DP_AUX_CH_CTL_INTERRUPT)
1331 trigger_aux_channel_interrupt(vgpu, offset);
1332 return 0;
1333 }
1334
mbctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1335 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1336 void *p_data, unsigned int bytes)
1337 {
1338 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1339 write_vreg(vgpu, offset, p_data, bytes);
1340 return 0;
1341 }
1342
vga_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1343 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1344 void *p_data, unsigned int bytes)
1345 {
1346 bool vga_disable;
1347
1348 write_vreg(vgpu, offset, p_data, bytes);
1349 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1350
1351 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1352 vga_disable ? "Disable" : "Enable");
1353 return 0;
1354 }
1355
read_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int sbi_offset)1356 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1357 unsigned int sbi_offset)
1358 {
1359 struct intel_vgpu_display *display = &vgpu->display;
1360 int num = display->sbi.number;
1361 int i;
1362
1363 for (i = 0; i < num; ++i)
1364 if (display->sbi.registers[i].offset == sbi_offset)
1365 break;
1366
1367 if (i == num)
1368 return 0;
1369
1370 return display->sbi.registers[i].value;
1371 }
1372
write_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int offset,u32 value)1373 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1374 unsigned int offset, u32 value)
1375 {
1376 struct intel_vgpu_display *display = &vgpu->display;
1377 int num = display->sbi.number;
1378 int i;
1379
1380 for (i = 0; i < num; ++i) {
1381 if (display->sbi.registers[i].offset == offset)
1382 break;
1383 }
1384
1385 if (i == num) {
1386 if (num == SBI_REG_MAX) {
1387 gvt_vgpu_err("SBI caching meets maximum limits\n");
1388 return;
1389 }
1390 display->sbi.number++;
1391 }
1392
1393 display->sbi.registers[i].offset = offset;
1394 display->sbi.registers[i].value = value;
1395 }
1396
sbi_data_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1397 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1398 void *p_data, unsigned int bytes)
1399 {
1400 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1401 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1402 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1403 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1404 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1405 sbi_offset);
1406 }
1407 read_vreg(vgpu, offset, p_data, bytes);
1408 return 0;
1409 }
1410
sbi_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1411 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1412 void *p_data, unsigned int bytes)
1413 {
1414 u32 data;
1415
1416 write_vreg(vgpu, offset, p_data, bytes);
1417 data = vgpu_vreg(vgpu, offset);
1418
1419 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1420 data |= SBI_READY;
1421
1422 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1423 data |= SBI_RESPONSE_SUCCESS;
1424
1425 vgpu_vreg(vgpu, offset) = data;
1426
1427 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1428 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1429 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1430 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1431
1432 write_virtual_sbi_register(vgpu, sbi_offset,
1433 vgpu_vreg_t(vgpu, SBI_DATA));
1434 }
1435 return 0;
1436 }
1437
1438 #define _vgtif_reg(x) \
1439 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1440
pvinfo_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1441 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1442 void *p_data, unsigned int bytes)
1443 {
1444 bool invalid_read = false;
1445
1446 read_vreg(vgpu, offset, p_data, bytes);
1447
1448 switch (offset) {
1449 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1450 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1451 invalid_read = true;
1452 break;
1453 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1454 _vgtif_reg(avail_rs.fence_num):
1455 if (offset + bytes >
1456 _vgtif_reg(avail_rs.fence_num) + 4)
1457 invalid_read = true;
1458 break;
1459 case 0x78010: /* vgt_caps */
1460 case 0x7881c:
1461 break;
1462 default:
1463 invalid_read = true;
1464 break;
1465 }
1466 if (invalid_read)
1467 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1468 offset, bytes, *(u32 *)p_data);
1469 vgpu->pv_notified = true;
1470 return 0;
1471 }
1472
handle_g2v_notification(struct intel_vgpu * vgpu,int notification)1473 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1474 {
1475 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1476 struct intel_vgpu_mm *mm;
1477 u64 *pdps;
1478
1479 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1480
1481 switch (notification) {
1482 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1483 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1484 fallthrough;
1485 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1486 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1487 return PTR_ERR_OR_ZERO(mm);
1488 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1489 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1490 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1491 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1492 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1493 case 1: /* Remove this in guest driver. */
1494 break;
1495 default:
1496 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1497 }
1498 return 0;
1499 }
1500
send_display_ready_uevent(struct intel_vgpu * vgpu,int ready)1501 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1502 {
1503 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
1504 char *env[3] = {NULL, NULL, NULL};
1505 char vmid_str[20];
1506 char display_ready_str[20];
1507
1508 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1509 env[0] = display_ready_str;
1510
1511 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1512 env[1] = vmid_str;
1513
1514 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1515 }
1516
pvinfo_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1517 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1518 void *p_data, unsigned int bytes)
1519 {
1520 u32 data = *(u32 *)p_data;
1521 bool invalid_write = false;
1522
1523 switch (offset) {
1524 case _vgtif_reg(display_ready):
1525 send_display_ready_uevent(vgpu, data ? 1 : 0);
1526 break;
1527 case _vgtif_reg(g2v_notify):
1528 handle_g2v_notification(vgpu, data);
1529 break;
1530 /* add xhot and yhot to handled list to avoid error log */
1531 case _vgtif_reg(cursor_x_hot):
1532 case _vgtif_reg(cursor_y_hot):
1533 case _vgtif_reg(pdp[0].lo):
1534 case _vgtif_reg(pdp[0].hi):
1535 case _vgtif_reg(pdp[1].lo):
1536 case _vgtif_reg(pdp[1].hi):
1537 case _vgtif_reg(pdp[2].lo):
1538 case _vgtif_reg(pdp[2].hi):
1539 case _vgtif_reg(pdp[3].lo):
1540 case _vgtif_reg(pdp[3].hi):
1541 case _vgtif_reg(execlist_context_descriptor_lo):
1542 case _vgtif_reg(execlist_context_descriptor_hi):
1543 break;
1544 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1545 invalid_write = true;
1546 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1547 break;
1548 default:
1549 invalid_write = true;
1550 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1551 offset, bytes, data);
1552 break;
1553 }
1554
1555 if (!invalid_write)
1556 write_vreg(vgpu, offset, p_data, bytes);
1557
1558 return 0;
1559 }
1560
pf_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1561 static int pf_write(struct intel_vgpu *vgpu,
1562 unsigned int offset, void *p_data, unsigned int bytes)
1563 {
1564 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1565 u32 val = *(u32 *)p_data;
1566
1567 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1568 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1569 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
1570 drm_WARN_ONCE(&i915->drm, true,
1571 "VM(%d): guest is trying to scaling a plane\n",
1572 vgpu->id);
1573 return 0;
1574 }
1575
1576 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1577 }
1578
power_well_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1579 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1580 unsigned int offset, void *p_data, unsigned int bytes)
1581 {
1582 write_vreg(vgpu, offset, p_data, bytes);
1583
1584 if (vgpu_vreg(vgpu, offset) &
1585 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1586 vgpu_vreg(vgpu, offset) |=
1587 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1588 else
1589 vgpu_vreg(vgpu, offset) &=
1590 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1591 return 0;
1592 }
1593
gen9_dbuf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1594 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1595 unsigned int offset, void *p_data, unsigned int bytes)
1596 {
1597 write_vreg(vgpu, offset, p_data, bytes);
1598
1599 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1600 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1601 else
1602 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1603
1604 return 0;
1605 }
1606
fpga_dbg_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1607 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1608 unsigned int offset, void *p_data, unsigned int bytes)
1609 {
1610 write_vreg(vgpu, offset, p_data, bytes);
1611
1612 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1613 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1614 return 0;
1615 }
1616
dma_ctrl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1617 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1618 void *p_data, unsigned int bytes)
1619 {
1620 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1621 u32 mode;
1622
1623 write_vreg(vgpu, offset, p_data, bytes);
1624 mode = vgpu_vreg(vgpu, offset);
1625
1626 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1627 drm_WARN_ONCE(&i915->drm, 1,
1628 "VM(%d): iGVT-g doesn't support GuC\n",
1629 vgpu->id);
1630 return 0;
1631 }
1632
1633 return 0;
1634 }
1635
gen9_trtte_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1636 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1637 void *p_data, unsigned int bytes)
1638 {
1639 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1640 u32 trtte = *(u32 *)p_data;
1641
1642 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1643 drm_WARN(&i915->drm, 1,
1644 "VM(%d): Use physical address for TRTT!\n",
1645 vgpu->id);
1646 return -EINVAL;
1647 }
1648 write_vreg(vgpu, offset, p_data, bytes);
1649
1650 return 0;
1651 }
1652
gen9_trtt_chicken_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1653 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1654 void *p_data, unsigned int bytes)
1655 {
1656 write_vreg(vgpu, offset, p_data, bytes);
1657 return 0;
1658 }
1659
dpll_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1660 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1661 void *p_data, unsigned int bytes)
1662 {
1663 u32 v = 0;
1664
1665 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1666 v |= (1 << 0);
1667
1668 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1669 v |= (1 << 8);
1670
1671 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1672 v |= (1 << 16);
1673
1674 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1675 v |= (1 << 24);
1676
1677 vgpu_vreg(vgpu, offset) = v;
1678
1679 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1680 }
1681
mailbox_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1682 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1683 void *p_data, unsigned int bytes)
1684 {
1685 u32 value = *(u32 *)p_data;
1686 u32 cmd = value & 0xff;
1687 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1688
1689 switch (cmd) {
1690 case GEN9_PCODE_READ_MEM_LATENCY:
1691 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1692 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1693 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1694 IS_COMETLAKE(vgpu->gvt->gt->i915)) {
1695 /**
1696 * "Read memory latency" command on gen9.
1697 * Below memory latency values are read
1698 * from skylake platform.
1699 */
1700 if (!*data0)
1701 *data0 = 0x1e1a1100;
1702 else
1703 *data0 = 0x61514b3d;
1704 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
1705 /**
1706 * "Read memory latency" command on gen9.
1707 * Below memory latency values are read
1708 * from Broxton MRB.
1709 */
1710 if (!*data0)
1711 *data0 = 0x16080707;
1712 else
1713 *data0 = 0x16161616;
1714 }
1715 break;
1716 case SKL_PCODE_CDCLK_CONTROL:
1717 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1718 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1719 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1720 IS_COMETLAKE(vgpu->gvt->gt->i915))
1721 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1722 break;
1723 case GEN6_PCODE_READ_RC6VIDS:
1724 *data0 |= 0x1;
1725 break;
1726 }
1727
1728 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1729 vgpu->id, value, *data0);
1730 /**
1731 * PCODE_READY clear means ready for pcode read/write,
1732 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1733 * always emulate as pcode read/write success and ready for access
1734 * anytime, since we don't touch real physical registers here.
1735 */
1736 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1737 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1738 }
1739
hws_pga_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1740 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1741 void *p_data, unsigned int bytes)
1742 {
1743 u32 value = *(u32 *)p_data;
1744 const struct intel_engine_cs *engine =
1745 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1746
1747 if (value != 0 &&
1748 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1749 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1750 offset, value);
1751 return -EINVAL;
1752 }
1753
1754 /*
1755 * Need to emulate all the HWSP register write to ensure host can
1756 * update the VM CSB status correctly. Here listed registers can
1757 * support BDW, SKL or other platforms with same HWSP registers.
1758 */
1759 if (unlikely(!engine)) {
1760 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1761 offset);
1762 return -EINVAL;
1763 }
1764 vgpu->hws_pga[engine->id] = value;
1765 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1766 vgpu->id, value, offset);
1767
1768 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1769 }
1770
skl_power_well_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1771 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1772 unsigned int offset, void *p_data, unsigned int bytes)
1773 {
1774 u32 v = *(u32 *)p_data;
1775
1776 if (IS_BROXTON(vgpu->gvt->gt->i915))
1777 v &= (1 << 31) | (1 << 29);
1778 else
1779 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1780 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1781 v |= (v >> 1);
1782
1783 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1784 }
1785
skl_lcpll_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1786 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1787 void *p_data, unsigned int bytes)
1788 {
1789 u32 v = *(u32 *)p_data;
1790
1791 /* other bits are MBZ. */
1792 v &= (1 << 31) | (1 << 30);
1793 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1794
1795 vgpu_vreg(vgpu, offset) = v;
1796
1797 return 0;
1798 }
1799
bxt_de_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1800 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1801 unsigned int offset, void *p_data, unsigned int bytes)
1802 {
1803 u32 v = *(u32 *)p_data;
1804
1805 if (v & BXT_DE_PLL_PLL_ENABLE)
1806 v |= BXT_DE_PLL_LOCK;
1807
1808 vgpu_vreg(vgpu, offset) = v;
1809
1810 return 0;
1811 }
1812
bxt_port_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1813 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1814 unsigned int offset, void *p_data, unsigned int bytes)
1815 {
1816 u32 v = *(u32 *)p_data;
1817
1818 if (v & PORT_PLL_ENABLE)
1819 v |= PORT_PLL_LOCK;
1820
1821 vgpu_vreg(vgpu, offset) = v;
1822
1823 return 0;
1824 }
1825
bxt_phy_ctl_family_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1826 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1827 unsigned int offset, void *p_data, unsigned int bytes)
1828 {
1829 u32 v = *(u32 *)p_data;
1830 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1831
1832 switch (offset) {
1833 case _PHY_CTL_FAMILY_EDP:
1834 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1835 break;
1836 case _PHY_CTL_FAMILY_DDI:
1837 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1838 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1839 break;
1840 }
1841
1842 vgpu_vreg(vgpu, offset) = v;
1843
1844 return 0;
1845 }
1846
bxt_port_tx_dw3_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1847 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1848 unsigned int offset, void *p_data, unsigned int bytes)
1849 {
1850 u32 v = vgpu_vreg(vgpu, offset);
1851
1852 v &= ~UNIQUE_TRANGE_EN_METHOD;
1853
1854 vgpu_vreg(vgpu, offset) = v;
1855
1856 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1857 }
1858
bxt_pcs_dw12_grp_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1859 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1860 unsigned int offset, void *p_data, unsigned int bytes)
1861 {
1862 u32 v = *(u32 *)p_data;
1863
1864 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1865 vgpu_vreg(vgpu, offset - 0x600) = v;
1866 vgpu_vreg(vgpu, offset - 0x800) = v;
1867 } else {
1868 vgpu_vreg(vgpu, offset - 0x400) = v;
1869 vgpu_vreg(vgpu, offset - 0x600) = v;
1870 }
1871
1872 vgpu_vreg(vgpu, offset) = v;
1873
1874 return 0;
1875 }
1876
bxt_gt_disp_pwron_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1877 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1878 unsigned int offset, void *p_data, unsigned int bytes)
1879 {
1880 u32 v = *(u32 *)p_data;
1881
1882 if (v & BIT(0)) {
1883 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1884 ~PHY_RESERVED;
1885 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1886 PHY_POWER_GOOD;
1887 }
1888
1889 if (v & BIT(1)) {
1890 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1891 ~PHY_RESERVED;
1892 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1893 PHY_POWER_GOOD;
1894 }
1895
1896
1897 vgpu_vreg(vgpu, offset) = v;
1898
1899 return 0;
1900 }
1901
edp_psr_imr_iir_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1902 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1903 unsigned int offset, void *p_data, unsigned int bytes)
1904 {
1905 vgpu_vreg(vgpu, offset) = 0;
1906 return 0;
1907 }
1908
1909 /*
1910 * FixMe:
1911 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1912 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1913 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1914 * these MI_BATCH_BUFFER.
1915 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1916 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1917 * The performance is still expected to be low, will need further improvement.
1918 */
bxt_ppat_low_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1919 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1920 void *p_data, unsigned int bytes)
1921 {
1922 u64 pat =
1923 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1924 GEN8_PPAT(1, 0) |
1925 GEN8_PPAT(2, 0) |
1926 GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1927 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1928 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1929 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1930 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1931
1932 vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1933
1934 return 0;
1935 }
1936
guc_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1937 static int guc_status_read(struct intel_vgpu *vgpu,
1938 unsigned int offset, void *p_data,
1939 unsigned int bytes)
1940 {
1941 /* keep MIA_IN_RESET before clearing */
1942 read_vreg(vgpu, offset, p_data, bytes);
1943 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1944 return 0;
1945 }
1946
mmio_read_from_hw(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1947 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1948 unsigned int offset, void *p_data, unsigned int bytes)
1949 {
1950 struct intel_gvt *gvt = vgpu->gvt;
1951 const struct intel_engine_cs *engine =
1952 intel_gvt_render_mmio_to_engine(gvt, offset);
1953
1954 /**
1955 * Read HW reg in following case
1956 * a. the offset isn't a ring mmio
1957 * b. the offset's ring is running on hw.
1958 * c. the offset is ring time stamp mmio
1959 */
1960
1961 if (!engine ||
1962 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1963 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1964 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
1965 mmio_hw_access_pre(gvt->gt);
1966 vgpu_vreg(vgpu, offset) =
1967 intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1968 mmio_hw_access_post(gvt->gt);
1969 }
1970
1971 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1972 }
1973
elsp_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1974 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1975 void *p_data, unsigned int bytes)
1976 {
1977 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1978 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1979 struct intel_vgpu_execlist *execlist;
1980 u32 data = *(u32 *)p_data;
1981 int ret = 0;
1982
1983 if (drm_WARN_ON(&i915->drm, !engine))
1984 return -EINVAL;
1985
1986 /*
1987 * Due to d3_entered is used to indicate skipping PPGTT invalidation on
1988 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
1989 * vGPU reset if in resuming.
1990 * In S0ix exit, the device power state also transite from D3 to D0 as
1991 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After
1992 * S0ix exit, all engines continue to work. However the d3_entered
1993 * remains set which will break next vGPU reset logic (miss the expected
1994 * PPGTT invalidation).
1995 * Engines can only work in D0. Thus the 1st elsp write gives GVT a
1996 * chance to clear d3_entered.
1997 */
1998 if (vgpu->d3_entered)
1999 vgpu->d3_entered = false;
2000
2001 execlist = &vgpu->submission.execlist[engine->id];
2002
2003 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
2004 if (execlist->elsp_dwords.index == 3) {
2005 ret = intel_vgpu_submit_execlist(vgpu, engine);
2006 if(ret)
2007 gvt_vgpu_err("fail submit workload on ring %s\n",
2008 engine->name);
2009 }
2010
2011 ++execlist->elsp_dwords.index;
2012 execlist->elsp_dwords.index &= 0x3;
2013 return ret;
2014 }
2015
ring_mode_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2016 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2017 void *p_data, unsigned int bytes)
2018 {
2019 u32 data = *(u32 *)p_data;
2020 const struct intel_engine_cs *engine =
2021 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
2022 bool enable_execlist;
2023 int ret;
2024
2025 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2026 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2027 IS_COMETLAKE(vgpu->gvt->gt->i915))
2028 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2029 write_vreg(vgpu, offset, p_data, bytes);
2030
2031 if (IS_MASKED_BITS_ENABLED(data, 1)) {
2032 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2033 return 0;
2034 }
2035
2036 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2037 IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
2038 IS_MASKED_BITS_ENABLED(data, 2)) {
2039 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2040 return 0;
2041 }
2042
2043 /* when PPGTT mode enabled, we will check if guest has called
2044 * pvinfo, if not, we will treat this guest as non-gvtg-aware
2045 * guest, and stop emulating its cfg space, mmio, gtt, etc.
2046 */
2047 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
2048 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
2049 !vgpu->pv_notified) {
2050 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2051 return 0;
2052 }
2053 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
2054 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
2055 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
2056
2057 gvt_dbg_core("EXECLIST %s on ring %s\n",
2058 (enable_execlist ? "enabling" : "disabling"),
2059 engine->name);
2060
2061 if (!enable_execlist)
2062 return 0;
2063
2064 ret = intel_vgpu_select_submission_ops(vgpu,
2065 engine->mask,
2066 INTEL_VGPU_EXECLIST_SUBMISSION);
2067 if (ret)
2068 return ret;
2069
2070 intel_vgpu_start_schedule(vgpu);
2071 }
2072 return 0;
2073 }
2074
gvt_reg_tlb_control_handler(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2075 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
2076 unsigned int offset, void *p_data, unsigned int bytes)
2077 {
2078 unsigned int id = 0;
2079
2080 write_vreg(vgpu, offset, p_data, bytes);
2081 vgpu_vreg(vgpu, offset) = 0;
2082
2083 switch (offset) {
2084 case 0x4260:
2085 id = RCS0;
2086 break;
2087 case 0x4264:
2088 id = VCS0;
2089 break;
2090 case 0x4268:
2091 id = VCS1;
2092 break;
2093 case 0x426c:
2094 id = BCS0;
2095 break;
2096 case 0x4270:
2097 id = VECS0;
2098 break;
2099 default:
2100 return -EINVAL;
2101 }
2102 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
2103
2104 return 0;
2105 }
2106
ring_reset_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2107 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
2108 unsigned int offset, void *p_data, unsigned int bytes)
2109 {
2110 u32 data;
2111
2112 write_vreg(vgpu, offset, p_data, bytes);
2113 data = vgpu_vreg(vgpu, offset);
2114
2115 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
2116 data |= RESET_CTL_READY_TO_RESET;
2117 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
2118 data &= ~RESET_CTL_READY_TO_RESET;
2119
2120 vgpu_vreg(vgpu, offset) = data;
2121 return 0;
2122 }
2123
csfe_chicken1_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2124 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
2125 unsigned int offset, void *p_data,
2126 unsigned int bytes)
2127 {
2128 u32 data = *(u32 *)p_data;
2129
2130 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2131 write_vreg(vgpu, offset, p_data, bytes);
2132
2133 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
2134 IS_MASKED_BITS_ENABLED(data, 0x8))
2135 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2136
2137 return 0;
2138 }
2139
2140 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
2141 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
2142 s, f, am, rm, d, r, w); \
2143 if (ret) \
2144 return ret; \
2145 } while (0)
2146
2147 #define MMIO_DH(reg, d, r, w) \
2148 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2149
2150 #define MMIO_DFH(reg, d, f, r, w) \
2151 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2152
2153 #define MMIO_GM(reg, d, r, w) \
2154 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2155
2156 #define MMIO_GM_RDR(reg, d, r, w) \
2157 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2158
2159 #define MMIO_RO(reg, d, f, rm, r, w) \
2160 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2161
2162 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
2163 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2164 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2165 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
2166 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2167 if (HAS_ENGINE(gvt->gt, VCS1)) \
2168 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
2169 } while (0)
2170
2171 #define MMIO_RING_DFH(prefix, d, f, r, w) \
2172 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2173
2174 #define MMIO_RING_GM(prefix, d, r, w) \
2175 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2176
2177 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
2178 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2179
2180 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
2181 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2182
init_generic_mmio_info(struct intel_gvt * gvt)2183 static int init_generic_mmio_info(struct intel_gvt *gvt)
2184 {
2185 struct drm_i915_private *dev_priv = gvt->gt->i915;
2186 int ret;
2187
2188 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
2189 intel_vgpu_reg_imr_handler);
2190
2191 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
2192 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
2193 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
2194
2195 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
2196
2197
2198 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
2199 gamw_echo_dev_rw_ia_write);
2200
2201 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2202 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2203 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2204
2205 #define RING_REG(base) _MMIO((base) + 0x28)
2206 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2207 #undef RING_REG
2208
2209 #define RING_REG(base) _MMIO((base) + 0x134)
2210 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2211 #undef RING_REG
2212
2213 #define RING_REG(base) _MMIO((base) + 0x6c)
2214 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
2215 #undef RING_REG
2216 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
2217
2218 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
2219 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
2220 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
2221
2222 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
2223 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
2224 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
2225 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
2226 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
2227
2228 /* RING MODE */
2229 #define RING_REG(base) _MMIO((base) + 0x29c)
2230 MMIO_RING_DFH(RING_REG, D_ALL,
2231 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
2232 ring_mode_mmio_write);
2233 #undef RING_REG
2234
2235 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2236 NULL, NULL);
2237 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2238 NULL, NULL);
2239 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
2240 mmio_read_from_hw, NULL);
2241 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
2242 mmio_read_from_hw, NULL);
2243
2244 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2245 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2246 NULL, NULL);
2247 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2248 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2249 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2250
2251 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2252 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2253 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2254 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
2255 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2256 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2257 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
2258 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2259 NULL, NULL);
2260 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2261 NULL, NULL);
2262 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2263 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2264 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2265 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2266 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2267 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2268 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2269 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2270 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2271 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2272
2273 /* display */
2274 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,
2275 pipeconf_mmio_write);
2276 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,
2277 pipeconf_mmio_write);
2278 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,
2279 pipeconf_mmio_write);
2280 MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,
2281 pipeconf_mmio_write);
2282 MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2283 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2284 reg50080_mmio_write);
2285 MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2286 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2287 reg50080_mmio_write);
2288 MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2289 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2290 reg50080_mmio_write);
2291 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2292 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2293 reg50080_mmio_write);
2294 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2295 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2296 reg50080_mmio_write);
2297 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2298 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2299 reg50080_mmio_write);
2300
2301 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2302 gmbus_mmio_write);
2303 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2304
2305 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2306 dp_aux_ch_ctl_mmio_write);
2307 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2308 dp_aux_ch_ctl_mmio_write);
2309 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2310 dp_aux_ch_ctl_mmio_write);
2311
2312 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2313
2314 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2315 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2316
2317 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2318 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2319 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2320 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2321 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2322 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2323 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2324 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2325 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2326 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2327 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2328 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2329 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2330 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2331 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2332 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2333
2334 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2335 PORTA_HOTPLUG_STATUS_MASK
2336 | PORTB_HOTPLUG_STATUS_MASK
2337 | PORTC_HOTPLUG_STATUS_MASK
2338 | PORTD_HOTPLUG_STATUS_MASK,
2339 NULL, NULL);
2340
2341 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2342 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2343 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2344 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2345 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2346
2347 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
2348 dp_aux_ch_ctl_mmio_write);
2349
2350 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2351 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2352 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2353 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2354 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2355
2356 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2357 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2358 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2359 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2360 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2361
2362 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2363 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2364 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2365 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2366 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2367
2368 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2369 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2370 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2371 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2372
2373 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2374 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2375 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2376 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2377 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2378 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2379 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2380 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2381 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2382 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2383 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2384 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2385 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2386
2387 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2388 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2389 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2390
2391 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2392 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2393
2394 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2395 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2396
2397 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2398 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2399 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2400 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2401 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2402 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2403
2404 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2405 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2406 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2407 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2408
2409 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2410 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2411 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2412
2413 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2414 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2415 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2416 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2417 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2418 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2419 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2420 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2421 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2422 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2423 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2424 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2425 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2426 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2427 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2428 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2429 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2430
2431 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2432 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
2433 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2434 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2435 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2436 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2437 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2438 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2439 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2440 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2441 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2442
2443 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2444 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2445 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2446
2447 return 0;
2448 }
2449
init_bdw_mmio_info(struct intel_gvt * gvt)2450 static int init_bdw_mmio_info(struct intel_gvt *gvt)
2451 {
2452 int ret;
2453
2454 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2455 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2456 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2457
2458 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2459 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2460 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2461
2462 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2463 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2464 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2465
2466 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2467 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2468 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2469
2470 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2471 intel_vgpu_reg_imr_handler);
2472 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2473 intel_vgpu_reg_ier_handler);
2474 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2475 intel_vgpu_reg_iir_handler);
2476
2477 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2478 intel_vgpu_reg_imr_handler);
2479 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2480 intel_vgpu_reg_ier_handler);
2481 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2482 intel_vgpu_reg_iir_handler);
2483
2484 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2485 intel_vgpu_reg_imr_handler);
2486 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2487 intel_vgpu_reg_ier_handler);
2488 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2489 intel_vgpu_reg_iir_handler);
2490
2491 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2492 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2493 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2494
2495 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2496 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2497 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2498
2499 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2500 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2501 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2502
2503 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2504 intel_vgpu_reg_master_irq_handler);
2505
2506 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2507 mmio_read_from_hw, NULL);
2508
2509 #define RING_REG(base) _MMIO((base) + 0xd0)
2510 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2511 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2512 ring_reset_ctl_write);
2513 #undef RING_REG
2514
2515 #define RING_REG(base) _MMIO((base) + 0x230)
2516 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2517 #undef RING_REG
2518
2519 #define RING_REG(base) _MMIO((base) + 0x234)
2520 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2521 NULL, NULL);
2522 #undef RING_REG
2523
2524 #define RING_REG(base) _MMIO((base) + 0x244)
2525 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2526 #undef RING_REG
2527
2528 #define RING_REG(base) _MMIO((base) + 0x370)
2529 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2530 #undef RING_REG
2531
2532 #define RING_REG(base) _MMIO((base) + 0x3a0)
2533 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2534 #undef RING_REG
2535
2536 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2537
2538 #define RING_REG(base) _MMIO((base) + 0x270)
2539 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2540 #undef RING_REG
2541
2542 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2543
2544 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2545
2546 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2547 NULL, NULL);
2548 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2549 NULL, NULL);
2550 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2551
2552 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2553 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2554 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2555 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2556 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2557
2558 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
2559 D_BDW_PLUS, NULL, force_nonpriv_write);
2560
2561 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2562
2563 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2564
2565 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2566 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2567 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2568 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2569
2570 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2571
2572 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2574 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2576 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2577 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2578 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2580 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2581 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2582 return 0;
2583 }
2584
init_skl_mmio_info(struct intel_gvt * gvt)2585 static int init_skl_mmio_info(struct intel_gvt *gvt)
2586 {
2587 int ret;
2588
2589 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2590 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2591 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2592 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
2593 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2594 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2595
2596 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2597 dp_aux_ch_ctl_mmio_write);
2598 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2599 dp_aux_ch_ctl_mmio_write);
2600 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2601 dp_aux_ch_ctl_mmio_write);
2602
2603 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2604
2605 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2606
2607 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2608 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2609 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2610 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2611 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2612 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2613
2614 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2615 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2616 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2617 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2618 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2619 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2620
2621 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2622 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2623 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2624 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2625 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2626 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2627
2628 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2629 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2630 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2631 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2632 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2633 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2634
2635 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2636 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2637 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2638 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2639
2640 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2641 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2642 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2643 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2644
2645 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2646 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2647 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2648 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2649
2650 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2651 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2652 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2653
2654 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2655 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2656 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2657
2658 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2659 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2660 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2661
2662 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2663 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2664 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2665
2666 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2667 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2668 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2669
2670 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2671 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2672 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2673 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2674
2675 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2676 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2677 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2678 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2679
2680 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2681 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2682 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2683 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2684
2685 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2686 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2687 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2688 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2689
2690 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2691 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2692 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2693 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2694
2695 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2696 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2697 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2698 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2699
2700 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2701 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2703 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2704
2705 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2706 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2708 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2709
2710 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2711 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2713 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2714
2715 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2716
2717 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2718 NULL, NULL);
2719 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2720 NULL, NULL);
2721
2722 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
2723 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2724 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2725 NULL, NULL);
2726
2727 /* TRTT */
2728 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2729 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2730 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2731 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2732 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2733 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
2734 NULL, gen9_trtte_write);
2735 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
2736 NULL, gen9_trtt_chicken_write);
2737
2738 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2739 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2740
2741 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
2742 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2743 NULL, csfe_chicken1_mmio_write);
2744 #undef CSFE_CHICKEN1_REG
2745 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2746 NULL, NULL);
2747 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2748 NULL, NULL);
2749
2750 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
2751 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2752
2753 return 0;
2754 }
2755
init_bxt_mmio_info(struct intel_gvt * gvt)2756 static int init_bxt_mmio_info(struct intel_gvt *gvt)
2757 {
2758 int ret;
2759
2760 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
2761 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
2762 NULL, bxt_phy_ctl_family_write);
2763 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
2764 NULL, bxt_phy_ctl_family_write);
2765 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
2766 NULL, bxt_port_pll_enable_write);
2767 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
2768 NULL, bxt_port_pll_enable_write);
2769 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
2770 bxt_port_pll_enable_write);
2771
2772 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
2773 NULL, bxt_pcs_dw12_grp_write);
2774 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
2775 bxt_port_tx_dw3_read, NULL);
2776 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
2777 NULL, bxt_pcs_dw12_grp_write);
2778 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
2779 bxt_port_tx_dw3_read, NULL);
2780 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
2781 NULL, bxt_pcs_dw12_grp_write);
2782 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
2783 bxt_port_tx_dw3_read, NULL);
2784 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
2785 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
2786 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2787 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
2788 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2789 0, 0, D_BXT, NULL, NULL);
2790 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2791 0, 0, D_BXT, NULL, NULL);
2792 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2793 0, 0, D_BXT, NULL, NULL);
2794 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2795 0, 0, D_BXT, NULL, NULL);
2796
2797 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2798
2799 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
2800
2801 return 0;
2802 }
2803
find_mmio_block(struct intel_gvt * gvt,unsigned int offset)2804 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2805 unsigned int offset)
2806 {
2807 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2808 int num = gvt->mmio.num_mmio_block;
2809 int i;
2810
2811 for (i = 0; i < num; i++, block++) {
2812 if (offset >= i915_mmio_reg_offset(block->offset) &&
2813 offset < i915_mmio_reg_offset(block->offset) + block->size)
2814 return block;
2815 }
2816 return NULL;
2817 }
2818
2819 /**
2820 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2821 * @gvt: GVT device
2822 *
2823 * This function is called at the driver unloading stage, to clean up the MMIO
2824 * information table of GVT device
2825 *
2826 */
intel_gvt_clean_mmio_info(struct intel_gvt * gvt)2827 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2828 {
2829 struct hlist_node *tmp;
2830 struct intel_gvt_mmio_info *e;
2831 int i;
2832
2833 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2834 kfree(e);
2835
2836 kfree(gvt->mmio.mmio_block);
2837 gvt->mmio.mmio_block = NULL;
2838 gvt->mmio.num_mmio_block = 0;
2839
2840 vfree(gvt->mmio.mmio_attribute);
2841 gvt->mmio.mmio_attribute = NULL;
2842 }
2843
handle_mmio(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2844 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2845 u32 size)
2846 {
2847 struct intel_gvt *gvt = iter->data;
2848 struct intel_gvt_mmio_info *info, *p;
2849 u32 start, end, i;
2850
2851 if (WARN_ON(!IS_ALIGNED(offset, 4)))
2852 return -EINVAL;
2853
2854 start = offset;
2855 end = offset + size;
2856
2857 for (i = start; i < end; i += 4) {
2858 p = intel_gvt_find_mmio_info(gvt, i);
2859 if (p) {
2860 WARN(1, "dup mmio definition offset %x\n", i);
2861
2862 /* We return -EEXIST here to make GVT-g load fail.
2863 * So duplicated MMIO can be found as soon as
2864 * possible.
2865 */
2866 return -EEXIST;
2867 }
2868
2869 info = kzalloc(sizeof(*info), GFP_KERNEL);
2870 if (!info)
2871 return -ENOMEM;
2872
2873 info->offset = i;
2874 info->read = intel_vgpu_default_mmio_read;
2875 info->write = intel_vgpu_default_mmio_write;
2876 INIT_HLIST_NODE(&info->node);
2877 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
2878 gvt->mmio.num_tracked_mmio++;
2879 }
2880 return 0;
2881 }
2882
handle_mmio_block(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2883 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter,
2884 u32 offset, u32 size)
2885 {
2886 struct intel_gvt *gvt = iter->data;
2887 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2888 void *ret;
2889
2890 ret = krealloc(block,
2891 (gvt->mmio.num_mmio_block + 1) * sizeof(*block),
2892 GFP_KERNEL);
2893 if (!ret)
2894 return -ENOMEM;
2895
2896 gvt->mmio.mmio_block = block = ret;
2897
2898 block += gvt->mmio.num_mmio_block;
2899
2900 memset(block, 0, sizeof(*block));
2901
2902 block->offset = _MMIO(offset);
2903 block->size = size;
2904
2905 gvt->mmio.num_mmio_block++;
2906
2907 return 0;
2908 }
2909
handle_mmio_cb(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2910 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2911 u32 size)
2912 {
2913 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))
2914 return handle_mmio(iter, offset, size);
2915 else
2916 return handle_mmio_block(iter, offset, size);
2917 }
2918
init_mmio_info(struct intel_gvt * gvt)2919 static int init_mmio_info(struct intel_gvt *gvt)
2920 {
2921 struct intel_gvt_mmio_table_iter iter = {
2922 .i915 = gvt->gt->i915,
2923 .data = gvt,
2924 .handle_mmio_cb = handle_mmio_cb,
2925 };
2926
2927 return intel_gvt_iterate_mmio_table(&iter);
2928 }
2929
init_mmio_block_handlers(struct intel_gvt * gvt)2930 static int init_mmio_block_handlers(struct intel_gvt *gvt)
2931 {
2932 struct gvt_mmio_block *block;
2933
2934 block = find_mmio_block(gvt, VGT_PVINFO_PAGE);
2935 if (!block) {
2936 WARN(1, "fail to assign handlers to mmio block %x\n",
2937 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));
2938 return -ENODEV;
2939 }
2940
2941 block->read = pvinfo_mmio_read;
2942 block->write = pvinfo_mmio_write;
2943
2944 return 0;
2945 }
2946
2947 /**
2948 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2949 * @gvt: GVT device
2950 *
2951 * This function is called at the initialization stage, to setup the MMIO
2952 * information table for GVT device
2953 *
2954 * Returns:
2955 * zero on success, negative if failed.
2956 */
intel_gvt_setup_mmio_info(struct intel_gvt * gvt)2957 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2958 {
2959 struct intel_gvt_device_info *info = &gvt->device_info;
2960 struct drm_i915_private *i915 = gvt->gt->i915;
2961 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2962 int ret;
2963
2964 gvt->mmio.mmio_attribute = vzalloc(size);
2965 if (!gvt->mmio.mmio_attribute)
2966 return -ENOMEM;
2967
2968 ret = init_mmio_info(gvt);
2969 if (ret)
2970 goto err;
2971
2972 ret = init_mmio_block_handlers(gvt);
2973 if (ret)
2974 goto err;
2975
2976 ret = init_generic_mmio_info(gvt);
2977 if (ret)
2978 goto err;
2979
2980 if (IS_BROADWELL(i915)) {
2981 ret = init_bdw_mmio_info(gvt);
2982 if (ret)
2983 goto err;
2984 } else if (IS_SKYLAKE(i915) ||
2985 IS_KABYLAKE(i915) ||
2986 IS_COFFEELAKE(i915) ||
2987 IS_COMETLAKE(i915)) {
2988 ret = init_bdw_mmio_info(gvt);
2989 if (ret)
2990 goto err;
2991 ret = init_skl_mmio_info(gvt);
2992 if (ret)
2993 goto err;
2994 } else if (IS_BROXTON(i915)) {
2995 ret = init_bdw_mmio_info(gvt);
2996 if (ret)
2997 goto err;
2998 ret = init_skl_mmio_info(gvt);
2999 if (ret)
3000 goto err;
3001 ret = init_bxt_mmio_info(gvt);
3002 if (ret)
3003 goto err;
3004 }
3005
3006 return 0;
3007 err:
3008 intel_gvt_clean_mmio_info(gvt);
3009 return ret;
3010 }
3011
3012 /**
3013 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3014 * @gvt: a GVT device
3015 * @handler: the handler
3016 * @data: private data given to handler
3017 *
3018 * Returns:
3019 * Zero on success, negative error code if failed.
3020 */
intel_gvt_for_each_tracked_mmio(struct intel_gvt * gvt,int (* handler)(struct intel_gvt * gvt,u32 offset,void * data),void * data)3021 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3022 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3023 void *data)
3024 {
3025 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3026 struct intel_gvt_mmio_info *e;
3027 int i, j, ret;
3028
3029 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3030 ret = handler(gvt, e->offset, data);
3031 if (ret)
3032 return ret;
3033 }
3034
3035 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3036 /* pvinfo data doesn't come from hw mmio */
3037 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3038 continue;
3039
3040 for (j = 0; j < block->size; j += 4) {
3041 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);
3042 if (ret)
3043 return ret;
3044 }
3045 }
3046 return 0;
3047 }
3048
3049 /**
3050 * intel_vgpu_default_mmio_read - default MMIO read handler
3051 * @vgpu: a vGPU
3052 * @offset: access offset
3053 * @p_data: data return buffer
3054 * @bytes: access data length
3055 *
3056 * Returns:
3057 * Zero on success, negative error code if failed.
3058 */
intel_vgpu_default_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3059 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3060 void *p_data, unsigned int bytes)
3061 {
3062 read_vreg(vgpu, offset, p_data, bytes);
3063 return 0;
3064 }
3065
3066 /**
3067 * intel_vgpu_default_mmio_write() - default MMIO write handler
3068 * @vgpu: a vGPU
3069 * @offset: access offset
3070 * @p_data: write data buffer
3071 * @bytes: access data length
3072 *
3073 * Returns:
3074 * Zero on success, negative error code if failed.
3075 */
intel_vgpu_default_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3076 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3077 void *p_data, unsigned int bytes)
3078 {
3079 write_vreg(vgpu, offset, p_data, bytes);
3080 return 0;
3081 }
3082
3083 /**
3084 * intel_vgpu_mask_mmio_write - write mask register
3085 * @vgpu: a vGPU
3086 * @offset: access offset
3087 * @p_data: write data buffer
3088 * @bytes: access data length
3089 *
3090 * Returns:
3091 * Zero on success, negative error code if failed.
3092 */
intel_vgpu_mask_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3093 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3094 void *p_data, unsigned int bytes)
3095 {
3096 u32 mask, old_vreg;
3097
3098 old_vreg = vgpu_vreg(vgpu, offset);
3099 write_vreg(vgpu, offset, p_data, bytes);
3100 mask = vgpu_vreg(vgpu, offset) >> 16;
3101 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3102 (vgpu_vreg(vgpu, offset) & mask);
3103
3104 return 0;
3105 }
3106
3107 /**
3108 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3109 * force-nopriv register
3110 *
3111 * @gvt: a GVT device
3112 * @offset: register offset
3113 *
3114 * Returns:
3115 * True if the register is in force-nonpriv whitelist;
3116 * False if outside;
3117 */
intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt * gvt,unsigned int offset)3118 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3119 unsigned int offset)
3120 {
3121 return in_whitelist(offset);
3122 }
3123
3124 /**
3125 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3126 * @vgpu: a vGPU
3127 * @offset: register offset
3128 * @pdata: data buffer
3129 * @bytes: data length
3130 * @is_read: read or write
3131 *
3132 * Returns:
3133 * Zero on success, negative error code if failed.
3134 */
intel_vgpu_mmio_reg_rw(struct intel_vgpu * vgpu,unsigned int offset,void * pdata,unsigned int bytes,bool is_read)3135 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3136 void *pdata, unsigned int bytes, bool is_read)
3137 {
3138 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
3139 struct intel_gvt *gvt = vgpu->gvt;
3140 struct intel_gvt_mmio_info *mmio_info;
3141 struct gvt_mmio_block *mmio_block;
3142 gvt_mmio_func func;
3143 int ret;
3144
3145 if (drm_WARN_ON(&i915->drm, bytes > 8))
3146 return -EINVAL;
3147
3148 /*
3149 * Handle special MMIO blocks.
3150 */
3151 mmio_block = find_mmio_block(gvt, offset);
3152 if (mmio_block) {
3153 func = is_read ? mmio_block->read : mmio_block->write;
3154 if (func)
3155 return func(vgpu, offset, pdata, bytes);
3156 goto default_rw;
3157 }
3158
3159 /*
3160 * Normal tracked MMIOs.
3161 */
3162 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
3163 if (!mmio_info) {
3164 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3165 goto default_rw;
3166 }
3167
3168 if (is_read)
3169 return mmio_info->read(vgpu, offset, pdata, bytes);
3170 else {
3171 u64 ro_mask = mmio_info->ro_mask;
3172 u32 old_vreg = 0;
3173 u64 data = 0;
3174
3175 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3176 old_vreg = vgpu_vreg(vgpu, offset);
3177 }
3178
3179 if (likely(!ro_mask))
3180 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3181 else if (!~ro_mask) {
3182 gvt_vgpu_err("try to write RO reg %x\n", offset);
3183 return 0;
3184 } else {
3185 /* keep the RO bits in the virtual register */
3186 memcpy(&data, pdata, bytes);
3187 data &= ~ro_mask;
3188 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3189 ret = mmio_info->write(vgpu, offset, &data, bytes);
3190 }
3191
3192 /* higher 16bits of mode ctl regs are mask bits for change */
3193 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3194 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3195
3196 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3197 | (vgpu_vreg(vgpu, offset) & mask);
3198 }
3199 }
3200
3201 return ret;
3202
3203 default_rw:
3204 return is_read ?
3205 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3206 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3207 }
3208
intel_gvt_restore_fence(struct intel_gvt * gvt)3209 void intel_gvt_restore_fence(struct intel_gvt *gvt)
3210 {
3211 struct intel_vgpu *vgpu;
3212 int i, id;
3213
3214 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3215 mmio_hw_access_pre(gvt->gt);
3216 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3217 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3218 mmio_hw_access_post(gvt->gt);
3219 }
3220 }
3221
mmio_pm_restore_handler(struct intel_gvt * gvt,u32 offset,void * data)3222 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)
3223 {
3224 struct intel_vgpu *vgpu = data;
3225 struct drm_i915_private *dev_priv = gvt->gt->i915;
3226
3227 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3228 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
3229
3230 return 0;
3231 }
3232
intel_gvt_restore_mmio(struct intel_gvt * gvt)3233 void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3234 {
3235 struct intel_vgpu *vgpu;
3236 int id;
3237
3238 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3239 mmio_hw_access_pre(gvt->gt);
3240 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3241 mmio_hw_access_post(gvt->gt);
3242 }
3243 }
3244