479 	struct intel_vgpu *vgpu;  member
520 	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
738 		    s->vgpu->id, s->engine->name,  in parser_exec_state_dump()
861 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_pdp_mmio_update_handler()  local
871 		mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);  in cmd_pdp_mmio_update_handler()
895 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_reg_handler()  local
896 	struct intel_gvt *gvt = vgpu->gvt;  in cmd_reg_handler()
955 	vreg = &vgpu_vreg(s->vgpu, offset);  in cmd_reg_handler()
986 				ret = mmio_info->write(s->vgpu, offset,  in cmd_reg_handler()
1017 		intel_gvt_read_gpa(s->vgpu,  in cmd_reg_handler()
1023 			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))  in cmd_reg_handler()
1024 				intel_vgpu_mask_mmio_write(vgpu,  in cmd_reg_handler()
1027 				vgpu_vreg(vgpu, offset) = data;  in cmd_reg_handler()
1095 	struct intel_gvt *gvt = s->vgpu->gvt;  in cmd_handler_lrm()
1124 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_srm()
1182 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_pipe_control()
1214 					hws_pga = s->vgpu->hws_pga[s->engine->id];  in cmd_handler_pipe_control()
1337 	struct intel_vgpu *vgpu = s->vgpu;  in skl_decode_mi_display_flip()  local
1401 		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);  in gen8_check_mi_display_flip()
1402 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &  in gen8_check_mi_display_flip()
1405 		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &  in gen8_check_mi_display_flip()
1407 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;  in gen8_check_mi_display_flip()
1425 	struct intel_vgpu *vgpu = s->vgpu;  in gen8_update_plane_mmio_from_mi_display_flip()  local
1427 	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),  in gen8_update_plane_mmio_from_mi_display_flip()
1430 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),  in gen8_update_plane_mmio_from_mi_display_flip()
1432 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),  in gen8_update_plane_mmio_from_mi_display_flip()
1435 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),  in gen8_update_plane_mmio_from_mi_display_flip()
1437 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),  in gen8_update_plane_mmio_from_mi_display_flip()
1442 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;  in gen8_update_plane_mmio_from_mi_display_flip()
1445 		intel_vgpu_trigger_virtual_event(vgpu, info->event);  in gen8_update_plane_mmio_from_mi_display_flip()
1447 		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);  in gen8_update_plane_mmio_from_mi_display_flip()
1479 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_handler_mi_display_flip()  local
1541 	struct intel_vgpu *vgpu = s->vgpu;  in get_gma_bb_from_cmd()  local
1542 	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in get_gma_bb_from_cmd()
1562 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_address_audit()  local
1563 	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;  in cmd_address_audit()
1578 	} else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {  in cmd_address_audit()
1597 			vgpu->id,  in cmd_address_audit()
1598 			vgpu_aperture_gmadr_base(vgpu),  in cmd_address_audit()
1599 			vgpu_aperture_gmadr_end(vgpu),  in cmd_address_audit()
1600 			vgpu_hidden_gmadr_base(vgpu),  in cmd_address_audit()
1601 			vgpu_hidden_gmadr_end(vgpu));  in cmd_address_audit()
1607 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_store_data_imm()
1640 	struct intel_vgpu *vgpu = s->vgpu;  in unexpected_cmd()  local
1664 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_op_2f()
1714 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;  in cmd_handler_mi_flush_dw()
1742 			hws_pga = s->vgpu->hws_pga[s->engine->id];  in cmd_handler_mi_flush_dw()
1765 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,  in copy_gma_to_hva()  argument
1784 		intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);  in copy_gma_to_hva()
1801 	    !(s->vgpu->scan_nonprivbb & s->engine->mask))  in batch_buffer_needs_scan()
1820 	struct intel_vgpu *vgpu = s->vgpu;  in find_bb_size()  local
1823 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;  in find_bb_size()
1834 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in find_bb_size()
1843 		if (copy_gma_to_hva(s->vgpu, mm,  in find_bb_size()
1846 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in find_bb_size()
1876 	struct intel_vgpu *vgpu = s->vgpu;  in audit_bb_end()  local
1880 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in audit_bb_end()
1899 	struct intel_vgpu *vgpu = s->vgpu;  in perform_bb_shadow()  local
1906 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;  in perform_bb_shadow()
1952 	ret = copy_gma_to_hva(s->vgpu, mm,  in perform_bb_shadow()
2000 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_handler_mi_batch_buffer_start()  local
2728 	struct intel_vgpu *vgpu = s->vgpu;  in cmd_parser_exec()  local
2739 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);  in cmd_parser_exec()
2751 	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,  in cmd_parser_exec()
2800 	struct intel_vgpu *vgpu = s->vgpu;  in command_scan()  local
2853 	s.vgpu = workload->vgpu;  in scan_workload()
2900 	s.vgpu = workload->vgpu;  in scan_wa_ctx()
2922 	struct intel_vgpu *vgpu = workload->vgpu;  in shadow_workload_ring_buffer()  local
2923 	struct intel_vgpu_submission *s = &vgpu->submission;  in shadow_workload_ring_buffer()
2959 		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,  in shadow_workload_ring_buffer()
2970 	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,  in shadow_workload_ring_buffer()
2982 	struct intel_vgpu *vgpu = workload->vgpu;  in intel_gvt_scan_and_shadow_ringbuffer()  local
3005 	struct intel_vgpu *vgpu = workload->vgpu;  in shadow_indirect_ctx()  local
3032 	ret = copy_gma_to_hva(workload->vgpu,  in shadow_indirect_ctx()
3033 				workload->vgpu->gtt.ggtt_mm,  in shadow_indirect_ctx()
3077 	struct intel_vgpu *vgpu = workload->vgpu;  in intel_gvt_scan_and_shadow_wa_ctx()  local
3104 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)  in intel_gvt_update_reg_whitelist()  argument
3107 	struct intel_gvt *gvt = vgpu->gvt;  in intel_gvt_update_reg_whitelist()
3132 		s.vgpu = vgpu;  in intel_gvt_update_reg_whitelist()
3161 	struct intel_vgpu *vgpu = workload->vgpu;  in intel_gvt_scan_engine_context()  local
3165 	struct intel_context *ce = vgpu->submission.shadow[ring_id];  in intel_gvt_scan_engine_context()
3184 	s.vgpu = workload->vgpu;  in intel_gvt_scan_engine_context()