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/linux/Documentation/translations/zh_CN/scsi/
H A Dscsi-parameters.rst30 advansys= [HW,SCSI]
33 aha152x= [HW,SCSI]
36 aha1542= [HW,SCSI]
39 aic7xxx= [HW,SCSI]
42 aic79xx= [HW,SCSI]
45 atascsi= [HW,SCSI]
48 BusLogic= [HW,SCSI]
52 gvp11= [HW,SCSI]
54 ips= [HW,SCSI] Adaptec / IBM ServeRAID 控制器
57 mac5380= [HW,SCSI]
[all …]
/linux/Documentation/scsi/
H A Dscsi-parameters.rst19 advansys= [HW,SCSI]
22 aha152x= [HW,SCSI]
25 aha1542= [HW,SCSI]
28 aic7xxx= [HW,SCSI]
31 aic79xx= [HW,SCSI]
34 atascsi= [HW,SCSI]
37 BusLogic= [HW,SCSI]
41 gvp11= [HW,SCSI]
43 ips= [HW,SCSI] Adaptec / IBM ServeRAID controller
46 mac5380= [HW,SCSI]
[all …]
/linux/Documentation/networking/device_drivers/ethernet/huawei/
H A Dhinic.rst35 specific HW details about HW data structure formats.
37 hinic_hwdev - Implement the HW details of the device and include the components
43 HW Interface:
49 Configuration Status Registers Area that describes the HW Registers on the
63 card by AEQs. Also set the addresses of the IO CMDQs in HW.
78 used to set the QPs addresses in HW. The commands completion events are
82 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
87 HW device:
90 HW device - de/constructs the HW Interface, the MGMT components on the
101 Port Commands - Send commands to the HW device for port management
[all …]
/linux/Documentation/watchdog/
H A Dmlx-wdt.rst13 There are 2 types of HW watchdog implementations.
16 Actual HW timeout can be defined as a power of 2 msec.
22 Actual HW timeout is defined in sec. and it's the same as
31 Type 1 HW watchdog implementation exist in old systems and
32 all new systems have type 2 HW watchdog.
33 Two types of HW implementation have also different register map.
35 Type 3 HW watchdog implementation can exist on all Mellanox systems
54 This mlx-wdt driver supports both HW watchdog implementations.
65 Access to HW registers is performed through a generic regmap interface.
/linux/Documentation/networking/dsa/
H A Dlan9303.rst21 interfaces (which is the default state of a DSA device). Due to HW limitations,
22 no HW MAC learning takes place in this mode.
24 When both user ports are joined to the same bridge, the normal HW MAC learning
25 is enabled. This means that unicast traffic is forwarded in HW. Broadcast and
26 multicast is flooded in HW. STP is also supported in this mode. The driver
37 - The HW does not support VLAN-specific fdb entries
/linux/Documentation/driver-api/iio/
H A Dhw-consumer.rst2 HW consumer
6 The Industrial I/O HW consumer offers a way to bond these IIO devices without
18 HW consumer setup
22 A typical IIO HW consumer setup looks like this::
/linux/drivers/crypto/intel/keembay/
H A DKconfig2 tristate "Support for Intel Keem Bay OCS AES/SM4 HW acceleration"
12 Provides HW acceleration for the following transformations:
20 bool "Support for Intel Keem Bay OCS AES/SM4 ECB HW acceleration"
31 bool "Support for Intel Keem Bay OCS AES/SM4 CTS HW acceleration"
43 tristate "Support for Intel Keem Bay OCS ECC HW acceleration"
62 tristate "Support for Intel Keem Bay OCS HCU HW acceleration"
/linux/Documentation/gpu/rfc/
H A Dcolor_pipeline.rst12 HW-supported HDR use-cases, as well as to provide support to
15 It is possible to support an HDR output on HW supporting the Colorspace
20 Most modern display HW offers various 1D LUTs, 3D LUTs, matrices, and other
22 implemented in fixed-function HW and therefore much more power efficient than
25 We would like to make use of this HW functionality to support complex color
26 transformations with no, or minimal CPU or shader load. The switch between HW
39 Drivers will then program their fixed-function HW accordingly to map from a
42 When fixed-function HW is not available the compositor will assemble a shader to
47 entirely separate concepts. On OSes where a HW vendor has no insight into
64 This means that a HW vendor can now no longer tune their driver to one
[all …]
/linux/net/tls/
H A DKconfig20 bool "Transport Layer Security HW offload"
27 Enable kernel support for HW offload of the TLS protocol.
36 Enable kernel support for legacy HW offload of the TLS protocol,
/linux/drivers/gpu/drm/sti/
H A DNOTES3 The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
19 - The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
20 Note that some stiH drivers support only a subset of thee HW IP.
37 2. DRM / HW mapping
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst159 This parameter changes the default HW FIFO Threshold control value.
218 the reception on chips older than the 3.50. New chips have an HW RX Watchdog
263 checks to the HW using MAC and PHY loopback mechanisms::
305 supported. This is done by looking at both the DMA HW capability register and
326 available at run-time by looking at the HW capability register. This means
328 PHYLIB stuff. In fact, the HW provides a subset of extended registers to
372 7) HW uses the GMAC core::
380 9) Core is able to perform TX Checksum and/or RX Checksum in HW::
385 11) Some HWs are not able to perform the csum in HW for over-sized frames due
440 necessary on some platforms (e.g. ST boxes) where the HW needs to have set
[all …]
/linux/Documentation/virt/kvm/devices/
H A Dxive.rst21 The KVM device exposes different MMIO ranges of the XIVE HW which
52 interrupts are from a different HW controller (PHB4) and the ESB
56 kvmppc_xive_clr_mapped() are called when the device HW irqs are
60 The handler will insert the ESB page corresponding to the HW
119 -ENXIO Could not allocate underlying HW interrupt
147 underlying HW interrupt failed
192 -EIO Configuration of the underlying HW failed
211 called the NVT. When a VP is not dispatched on a HW processor
212 thread, this structure can be updated by HW if the VP is the target
/linux/Documentation/arch/powerpc/
H A Dcpu_families.rst168 - e6500 adds HW loaded indirect TLB entries.
201 | e6500 (HW TLB) (Multithreaded) |
208 - Book3E, software loaded TLB + HW loaded indirect TLB entries.
/linux/Documentation/arch/x86/
H A Dtsx_async_abort.rst69 …0 0 0 HW default Yes Same as MDS Same as MDS
71 …0 1 0 HW default No Need ucode update Need ucode up…
84 … 0 0 0 HW default Yes Same as MDS Same as MDS
86 …0 1 0 HW default No Need ucode update Need ucode up…
99 …0 0 0 HW default Yes Same as MDS Same as MDS
101 …0 1 0 HW default No Need ucode update Need ucode up…
/linux/Documentation/devicetree/bindings/reset/
H A Dreset.txt21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-jaguar-pre-ict-tester.dtso79 * but GPIO3_C6 would catch this HW soldering issue.
92 * the loop doesn't exist on HW (soldering issue on
101 * but GPIO3_C6 would catch this HW soldering issue.
135 * the loop doesn't exist on HW (soldering issue on
145 * the loop doesn't exist on HW (soldering issue on
155 * the loop doesn't exist on HW (soldering issue on
165 * the loop doesn't exist on HW (soldering issue on
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_utils_fw.c18 #define hw_atl2_shared_buffer_write(HW, ITEM, VARIABLE) \ argument
25 hw_atl2_mif_shared_buf_write(HW,\
30 #define hw_atl2_shared_buffer_get(HW, ITEM, VARIABLE) \ argument
37 hw_atl2_mif_shared_buf_get(HW, \
46 #define hw_atl2_shared_buffer_read(HW, ITEM, VARIABLE) \ argument
55 hw_atl2_mif_shared_buf_read(HW, \
60 #define hw_atl2_shared_buffer_read_safe(HW, ITEM, DATA) \ argument
68 hw_atl2_shared_buffer_read_block((HW), \
/linux/Documentation/devicetree/bindings/arc/
H A Dpct.txt8 * The ARC 700 PCT does not support interrupts; although HW events may be
9 counted, the HW events themselves cannot serve as a trigger for a sample.
/linux/drivers/clk/bcm/
H A Dclk-kona.h48 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
157 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
169 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
199 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt9 entries in properties are marked as optional, or only required in specific HW
28 The EQOS transmit path clock. The HW signal name is clk_tx_i.
33 The EQOS receive path clock. The HW signal name is clk_rx_i.
44 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
48 separate clock for the master and slave bus interfaces. The HW signal name
51 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
92 - "eqos". The reset to the entire module. The HW signal name is hreset_n
/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt21 HW Appropriate hardware is enabled.
110 acpi= [HW,ACPI,X86,ARM64,RISCV64,EARLY]
143 acpi_backlight= [HW,ACPI]
158 acpica_no_return_repair [HW, ACPI]
166 acpi.debug_layer= [HW,ACPI,ACPI_DEBUG]
167 acpi.debug_level= [HW,ACPI,ACPI_DEBUG]
216 acpi_force_table_verification [HW,ACPI,EARLY]
221 acpi_irq_balance [HW,ACPI]
225 acpi_irq_nobalance [HW,ACPI]
229 acpi_irq_isa= [HW,ACPI] If irq_balance, mark listed IRQs used by ISA
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g044c2-smarc.dts24 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
32 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
/linux/drivers/mmc/core/
H A DKconfig6 tristate "HW reset support for eMMC"
17 tristate "HW reset support for SD8787 BT + Wifi module"
27 tristate "Simple HW reset support for MMC"
/linux/Documentation/userspace-api/
H A Diommufd.rst67 faults using the IOMMU HW's PRI (Page Request Interface). This queue object
74 passed to or shared with a VM. It may be some HW-accelerated virtualization
86 to support some HW-accelerated virtualization features. So, a vIOMMU object
121 page faults that should go through IOMMUFD_OBJ_FAULT) and HW-specific events.
128 of IOMMU's virtualization features, for the IOMMU HW to directly read or write
129 the virtual queue memory owned by a guest OS. This HW-acceleration feature can
130 allow VM to work with the IOMMU HW directly without a VM Exit, so as to reduce
131 overhead from the hypercalls. Along with the HW QUEUE object, iommufd provides
134 guest OS to directly control the allocated HW QUEUE. Thus, when allocating a
135 HW QUEUE, the VMM must request a pair of mmap info (offset/length) and pass in
[all …]
/linux/drivers/gpu/drm/i915/
H A DKconfig.profile61 an arbitration point and yield to HW before the timer expires, the
62 HW will be reset to allow the more important context to execute.
79 current context does not hit an arbitration point and yield to HW
80 before the timer expires, the HW will be reset to allow the more

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