1*ff61f079SJonathan Corbet.. SPDX-License-Identifier: GPL-2.0 2*ff61f079SJonathan Corbet 3*ff61f079SJonathan CorbetTSX Async Abort (TAA) mitigation 4*ff61f079SJonathan Corbet================================ 5*ff61f079SJonathan Corbet 6*ff61f079SJonathan Corbet.. _tsx_async_abort: 7*ff61f079SJonathan Corbet 8*ff61f079SJonathan CorbetOverview 9*ff61f079SJonathan Corbet-------- 10*ff61f079SJonathan Corbet 11*ff61f079SJonathan CorbetTSX Async Abort (TAA) is a side channel attack on internal buffers in some 12*ff61f079SJonathan CorbetIntel processors similar to Microachitectural Data Sampling (MDS). In this 13*ff61f079SJonathan Corbetcase certain loads may speculatively pass invalid data to dependent operations 14*ff61f079SJonathan Corbetwhen an asynchronous abort condition is pending in a Transactional 15*ff61f079SJonathan CorbetSynchronization Extensions (TSX) transaction. This includes loads with no 16*ff61f079SJonathan Corbetfault or assist condition. Such loads may speculatively expose stale data from 17*ff61f079SJonathan Corbetthe same uarch data structures as in MDS, with same scope of exposure i.e. 18*ff61f079SJonathan Corbetsame-thread and cross-thread. This issue affects all current processors that 19*ff61f079SJonathan Corbetsupport TSX. 20*ff61f079SJonathan Corbet 21*ff61f079SJonathan CorbetMitigation strategy 22*ff61f079SJonathan Corbet------------------- 23*ff61f079SJonathan Corbet 24*ff61f079SJonathan Corbeta) TSX disable - one of the mitigations is to disable TSX. A new MSR 25*ff61f079SJonathan CorbetIA32_TSX_CTRL will be available in future and current processors after 26*ff61f079SJonathan Corbetmicrocode update which can be used to disable TSX. In addition, it 27*ff61f079SJonathan Corbetcontrols the enumeration of the TSX feature bits (RTM and HLE) in CPUID. 28*ff61f079SJonathan Corbet 29*ff61f079SJonathan Corbetb) Clear CPU buffers - similar to MDS, clearing the CPU buffers mitigates this 30*ff61f079SJonathan Corbetvulnerability. More details on this approach can be found in 31*ff61f079SJonathan Corbet:ref:`Documentation/admin-guide/hw-vuln/mds.rst <mds>`. 32*ff61f079SJonathan Corbet 33*ff61f079SJonathan CorbetKernel internal mitigation modes 34*ff61f079SJonathan Corbet-------------------------------- 35*ff61f079SJonathan Corbet 36*ff61f079SJonathan Corbet ============= ============================================================ 37*ff61f079SJonathan Corbet off Mitigation is disabled. Either the CPU is not affected or 38*ff61f079SJonathan Corbet tsx_async_abort=off is supplied on the kernel command line. 39*ff61f079SJonathan Corbet 40*ff61f079SJonathan Corbet tsx disabled Mitigation is enabled. TSX feature is disabled by default at 41*ff61f079SJonathan Corbet bootup on processors that support TSX control. 42*ff61f079SJonathan Corbet 43*ff61f079SJonathan Corbet verw Mitigation is enabled. CPU is affected and MD_CLEAR is 44*ff61f079SJonathan Corbet advertised in CPUID. 45*ff61f079SJonathan Corbet 46*ff61f079SJonathan Corbet ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not 47*ff61f079SJonathan Corbet advertised in CPUID. That is mainly for virtualization 48*ff61f079SJonathan Corbet scenarios where the host has the updated microcode but the 49*ff61f079SJonathan Corbet hypervisor does not expose MD_CLEAR in CPUID. It's a best 50*ff61f079SJonathan Corbet effort approach without guarantee. 51*ff61f079SJonathan Corbet ============= ============================================================ 52*ff61f079SJonathan Corbet 53*ff61f079SJonathan CorbetIf the CPU is affected and the "tsx_async_abort" kernel command line parameter is 54*ff61f079SJonathan Corbetnot provided then the kernel selects an appropriate mitigation depending on the 55*ff61f079SJonathan Corbetstatus of RTM and MD_CLEAR CPUID bits. 56*ff61f079SJonathan Corbet 57*ff61f079SJonathan CorbetBelow tables indicate the impact of tsx=on|off|auto cmdline options on state of 58*ff61f079SJonathan CorbetTAA mitigation, VERW behavior and TSX feature for various combinations of 59*ff61f079SJonathan CorbetMSR_IA32_ARCH_CAPABILITIES bits. 60*ff61f079SJonathan Corbet 61*ff61f079SJonathan Corbet1. "tsx=off" 62*ff61f079SJonathan Corbet 63*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 64*ff61f079SJonathan CorbetMSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=off 65*ff61f079SJonathan Corbet---------------------------------- ------------------------------------------------------------------------- 66*ff61f079SJonathan CorbetTAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation 67*ff61f079SJonathan Corbet after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full 68*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 69*ff61f079SJonathan Corbet 0 0 0 HW default Yes Same as MDS Same as MDS 70*ff61f079SJonathan Corbet 0 0 1 Invalid case Invalid case Invalid case Invalid case 71*ff61f079SJonathan Corbet 0 1 0 HW default No Need ucode update Need ucode update 72*ff61f079SJonathan Corbet 0 1 1 Disabled Yes TSX disabled TSX disabled 73*ff61f079SJonathan Corbet 1 X 1 Disabled X None needed None needed 74*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 75*ff61f079SJonathan Corbet 76*ff61f079SJonathan Corbet2. "tsx=on" 77*ff61f079SJonathan Corbet 78*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 79*ff61f079SJonathan CorbetMSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=on 80*ff61f079SJonathan Corbet---------------------------------- ------------------------------------------------------------------------- 81*ff61f079SJonathan CorbetTAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation 82*ff61f079SJonathan Corbet after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full 83*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 84*ff61f079SJonathan Corbet 0 0 0 HW default Yes Same as MDS Same as MDS 85*ff61f079SJonathan Corbet 0 0 1 Invalid case Invalid case Invalid case Invalid case 86*ff61f079SJonathan Corbet 0 1 0 HW default No Need ucode update Need ucode update 87*ff61f079SJonathan Corbet 0 1 1 Enabled Yes None Same as MDS 88*ff61f079SJonathan Corbet 1 X 1 Enabled X None needed None needed 89*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 90*ff61f079SJonathan Corbet 91*ff61f079SJonathan Corbet3. "tsx=auto" 92*ff61f079SJonathan Corbet 93*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 94*ff61f079SJonathan CorbetMSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=auto 95*ff61f079SJonathan Corbet---------------------------------- ------------------------------------------------------------------------- 96*ff61f079SJonathan CorbetTAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation 97*ff61f079SJonathan Corbet after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full 98*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 99*ff61f079SJonathan Corbet 0 0 0 HW default Yes Same as MDS Same as MDS 100*ff61f079SJonathan Corbet 0 0 1 Invalid case Invalid case Invalid case Invalid case 101*ff61f079SJonathan Corbet 0 1 0 HW default No Need ucode update Need ucode update 102*ff61f079SJonathan Corbet 0 1 1 Disabled Yes TSX disabled TSX disabled 103*ff61f079SJonathan Corbet 1 X 1 Enabled X None needed None needed 104*ff61f079SJonathan Corbet========= ========= ============ ============ ============== =================== ====================== 105*ff61f079SJonathan Corbet 106*ff61f079SJonathan CorbetIn the tables, TSX_CTRL_MSR is a new bit in MSR_IA32_ARCH_CAPABILITIES that 107*ff61f079SJonathan Corbetindicates whether MSR_IA32_TSX_CTRL is supported. 108*ff61f079SJonathan Corbet 109*ff61f079SJonathan CorbetThere are two control bits in IA32_TSX_CTRL MSR: 110*ff61f079SJonathan Corbet 111*ff61f079SJonathan Corbet Bit 0: When set it disables the Restricted Transactional Memory (RTM) 112*ff61f079SJonathan Corbet sub-feature of TSX (will force all transactions to abort on the 113*ff61f079SJonathan Corbet XBEGIN instruction). 114*ff61f079SJonathan Corbet 115*ff61f079SJonathan Corbet Bit 1: When set it disables the enumeration of the RTM and HLE feature 116*ff61f079SJonathan Corbet (i.e. it will make CPUID(EAX=7).EBX{bit4} and 117*ff61f079SJonathan Corbet CPUID(EAX=7).EBX{bit11} read as 0). 118