1What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink 2Date: November 2014 3KernelVersion: 3.19 4Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 5Description: (RW) Add/remove a sink from a trace path. There can be multiple 6 source for a single sink. 7 8 ex:: 9 10 echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink 11 12What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr 13Date: November 2014 14KernelVersion: 3.19 15Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 16Description: (RW) Disables write access to the Trace RAM by stopping the 17 formatter after a defined number of words have been stored 18 following the trigger event. The number of 32-bit words written 19 into the Trace RAM following the trigger event is equal to the 20 value stored in this register+1 (from ARM ETB-TRM). 21 22What: /sys/bus/coresight/devices/<memory_map>.etb/label 23Date: Aug 2025 24KernelVersion 6.18 25Contact: Mao Jinlong <quic_jinlmao@quicinc.com> 26Description: (Read) Show hardware context information of device. 27 28What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp 29Date: March 2016 30KernelVersion: 4.7 31Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 32Description: (Read) Defines the depth, in words, of the trace RAM in powers of 33 2. The value is read directly from HW register RDP, 0x004. 34 35What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts 36Date: March 2016 37KernelVersion: 4.7 38Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 39Description: (Read) Shows the value held by the ETB status register. The value 40 is read directly from HW register STS, 0x00C. 41 42What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp 43Date: March 2016 44KernelVersion: 4.7 45Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 46Description: (Read) Shows the value held by the ETB RAM Read Pointer register 47 that is used to read entries from the Trace RAM over the APB 48 interface. The value is read directly from HW register RRP, 49 0x014. 50 51What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp 52Date: March 2016 53KernelVersion: 4.7 54Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 55Description: (Read) Shows the value held by the ETB RAM Write Pointer register 56 that is used to sets the write pointer to write entries from 57 the CoreSight bus into the Trace RAM. The value is read directly 58 from HW register RWP, 0x018. 59 60What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg 61Date: March 2016 62KernelVersion: 4.7 63Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 64Description: (Read) Similar to "trigger_cntr" above except that this value is 65 read directly from HW register TRG, 0x01C. 66 67What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl 68Date: March 2016 69KernelVersion: 4.7 70Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 71Description: (Read) Shows the value held by the ETB Control register. The value 72 is read directly from HW register CTL, 0x020. 73 74What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr 75Date: March 2016 76KernelVersion: 4.7 77Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 78Description: (Read) Shows the value held by the ETB Formatter and Flush Status 79 register. The value is read directly from HW register FFSR, 80 0x300. 81 82What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr 83Date: March 2016 84KernelVersion: 4.7 85Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 86Description: (Read) Shows the value held by the ETB Formatter and Flush Control 87 register. The value is read directly from HW register FFCR, 88 0x304. 89