Lines Matching refs:HW
159 This parameter changes the default HW FIFO Threshold control value.
218 the reception on chips older than the 3.50. New chips have an HW RX Watchdog
263 checks to the HW using MAC and PHY loopback mechanisms::
305 supported. This is done by looking at both the DMA HW capability register and
326 available at run-time by looking at the HW capability register. This means
328 PHYLIB stuff. In fact, the HW provides a subset of extended registers to
372 7) HW uses the GMAC core::
380 9) Core is able to perform TX Checksum and/or RX Checksum in HW::
385 11) Some HWs are not able to perform the csum in HW for over-sized frames due
440 necessary on some platforms (e.g. ST boxes) where the HW needs to have set
447 26) Perform HW setup of the bus. For example, on some ST platforms this field
470 30) HW uses GMAC>4 cores::
474 31) HW is sun8i based::
494 36) HW uses XGMAC>2.10 cores::
664 HW Capabilities
667 Note that, starting from new chips, where it is available the HW capability
669 understand if EEE, HW csum, PTP, enhanced descriptor etc are actually
670 available. As strategy adopted in this driver, the information from the HW
690 - ``dma_cap``: To show the HW Capabilities