1237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/enable_source 2237483aaSPratik PatelDate: April 2016 3237483aaSPratik PatelKernelVersion: 4.7 4237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5237483aaSPratik PatelDescription: (RW) Enable/disable tracing on this specific trace macrocell. 6237483aaSPratik Patel Enabling the trace macrocell implies it has been configured 7237483aaSPratik Patel properly and a sink has been identified for it. The path 8237483aaSPratik Patel of coresight components linking the source to the sink is 9237483aaSPratik Patel configured and managed automatically by the coresight framework. 10237483aaSPratik Patel 11237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable 12237483aaSPratik PatelDate: April 2016 13237483aaSPratik PatelKernelVersion: 4.7 14237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 15237483aaSPratik PatelDescription: (RW) Provides access to the HW event enable register, used in 16237483aaSPratik Patel conjunction with HW event bank select register. 17237483aaSPratik Patel 18237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select 19237483aaSPratik PatelDate: April 2016 20237483aaSPratik PatelKernelVersion: 4.7 21237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 22237483aaSPratik PatelDescription: (RW) Gives access to the HW event block select register 23237483aaSPratik Patel (STMHEBSR) in order to configure up to 256 channels. Used in 24237483aaSPratik Patel conjunction with "hwevent_enable" register as described above. 25237483aaSPratik Patel 26237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_enable 27237483aaSPratik PatelDate: April 2016 28237483aaSPratik PatelKernelVersion: 4.7 29237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 30237483aaSPratik PatelDescription: (RW) Provides access to the stimulus port enable register 31237483aaSPratik Patel (STMSPER). Used in conjunction with "port_select" described 32237483aaSPratik Patel below. 33237483aaSPratik Patel 34237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/port_select 35237483aaSPratik PatelDate: April 2016 36237483aaSPratik PatelKernelVersion: 4.7 37237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 38237483aaSPratik PatelDescription: (RW) Used to determine which bank of stimulus port bit in 39237483aaSPratik Patel register STMSPER (see above) apply to. 40237483aaSPratik Patel 41237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/status 42237483aaSPratik PatelDate: April 2016 43237483aaSPratik PatelKernelVersion: 4.7 44237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 45*4119f0dfSMauro Carvalho ChehabDescription: (Read) List various control and status registers. The specific 46237483aaSPratik Patel layout and content is driver specific. 47237483aaSPratik Patel 48237483aaSPratik PatelWhat: /sys/bus/coresight/devices/<memory_map>.stm/traceid 49237483aaSPratik PatelDate: April 2016 50237483aaSPratik PatelKernelVersion: 4.7 51237483aaSPratik PatelContact: Mathieu Poirier <mathieu.poirier@linaro.org> 52237483aaSPratik PatelDescription: (RW) Holds the trace ID that will appear in the trace stream 53237483aaSPratik Patel coming from this trace entity. 54