xref: /linux/Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10 (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940)
17a25ec8eSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/enable_sink
27a25ec8eSMathieu PoirierDate:		November 2014
37a25ec8eSMathieu PoirierKernelVersion:	3.19
47a25ec8eSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
57a25ec8eSMathieu PoirierDescription:	(RW) Add/remove a sink from a trace path.  There can be multiple
67a25ec8eSMathieu Poirier		source for a single sink.
754a19b4dSMauro Carvalho Chehab
854a19b4dSMauro Carvalho Chehab		ex::
954a19b4dSMauro Carvalho Chehab
1054a19b4dSMauro Carvalho Chehab		  echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
117a25ec8eSMathieu Poirier
127a25ec8eSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
137a25ec8eSMathieu PoirierDate:		November 2014
147a25ec8eSMathieu PoirierKernelVersion:	3.19
157a25ec8eSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
167a25ec8eSMathieu PoirierDescription:	(RW) Disables write access to the Trace RAM by stopping the
177a25ec8eSMathieu Poirier		formatter after a defined number of words have been stored
187a25ec8eSMathieu Poirier		following the trigger event. The number of 32-bit words written
197a25ec8eSMathieu Poirier		into the Trace RAM following the trigger event is equal to the
207a25ec8eSMathieu Poirier		value stored in this register+1 (from ARM ETB-TRM).
21ad352acbSMathieu Poirier
22*01f96b81SMao JinlongWhat:           /sys/bus/coresight/devices/<memory_map>.etb/label
23*01f96b81SMao JinlongDate:           Aug 2025
24*01f96b81SMao JinlongKernelVersion   6.18
25*01f96b81SMao JinlongContact:        Mao Jinlong <quic_jinlmao@quicinc.com>
26*01f96b81SMao JinlongDescription:    (Read) Show hardware context information of device.
27*01f96b81SMao Jinlong
28ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
29ad352acbSMathieu PoirierDate:		March 2016
30ad352acbSMathieu PoirierKernelVersion:	4.7
31ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
324119f0dfSMauro Carvalho ChehabDescription:	(Read) Defines the depth, in words, of the trace RAM in powers of
33ad352acbSMathieu Poirier		2.  The value is read directly from HW register RDP, 0x004.
34ad352acbSMathieu Poirier
35ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
36ad352acbSMathieu PoirierDate:		March 2016
37ad352acbSMathieu PoirierKernelVersion:	4.7
38ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
394119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB status register.  The value
40ad352acbSMathieu Poirier		is read directly from HW register STS, 0x00C.
41ad352acbSMathieu Poirier
42ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
43ad352acbSMathieu PoirierDate:		March 2016
44ad352acbSMathieu PoirierKernelVersion:	4.7
45ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
464119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB RAM Read Pointer register
47ad352acbSMathieu Poirier		that is used to read entries from the Trace RAM over the APB
48ad352acbSMathieu Poirier		interface.  The value is read directly from HW register RRP,
49ad352acbSMathieu Poirier		0x014.
50ad352acbSMathieu Poirier
51ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
52ad352acbSMathieu PoirierDate:		March 2016
53ad352acbSMathieu PoirierKernelVersion:	4.7
54ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
554119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB RAM Write Pointer register
56ad352acbSMathieu Poirier		that is used to sets the write pointer to write entries from
57ad352acbSMathieu Poirier		the CoreSight bus into the Trace RAM. The value is read directly
58ad352acbSMathieu Poirier		from HW register RWP, 0x018.
59ad352acbSMathieu Poirier
60ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
61ad352acbSMathieu PoirierDate:		March 2016
62ad352acbSMathieu PoirierKernelVersion:	4.7
63ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
644119f0dfSMauro Carvalho ChehabDescription:	(Read) Similar to "trigger_cntr" above except that this value is
65ad352acbSMathieu Poirier		read directly from HW register TRG, 0x01C.
66ad352acbSMathieu Poirier
67ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
68ad352acbSMathieu PoirierDate:		March 2016
69ad352acbSMathieu PoirierKernelVersion:	4.7
70ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
714119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB Control register. The value
72ad352acbSMathieu Poirier		is read directly from HW register CTL, 0x020.
73ad352acbSMathieu Poirier
74ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
75ad352acbSMathieu PoirierDate:		March 2016
76ad352acbSMathieu PoirierKernelVersion:	4.7
77ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
784119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB Formatter and Flush Status
79ad352acbSMathieu Poirier		register.  The value is read directly from HW register FFSR,
80ad352acbSMathieu Poirier		0x300.
81ad352acbSMathieu Poirier
82ad352acbSMathieu PoirierWhat:		/sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
83ad352acbSMathieu PoirierDate:		March 2016
84ad352acbSMathieu PoirierKernelVersion:	4.7
85ad352acbSMathieu PoirierContact:	Mathieu Poirier <mathieu.poirier@linaro.org>
864119f0dfSMauro Carvalho ChehabDescription:	(Read) Shows the value held by the ETB Formatter and Flush Control
87ad352acbSMathieu Poirier		register.  The value is read directly from HW register FFCR,
88ad352acbSMathieu Poirier		0x304.
89