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Searched refs:RegVT (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1718 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1730 if (RegVT == MVT::i8) in LowerFormalArguments()
1732 else if (RegVT == MVT::i16) in LowerFormalArguments()
1734 else if (RegVT == MVT::i32) in LowerFormalArguments()
1736 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
1738 else if (RegVT == MVT::f16) in LowerFormalArguments()
1740 else if (RegVT == MVT::f32) in LowerFormalArguments()
1742 else if (RegVT == MVT::f64) in LowerFormalArguments()
1744 else if (RegVT == MVT::f80) in LowerFormalArguments()
1746 else if (RegVT == MVT::f128) in LowerFormalArguments()
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H A DX86ISelLowering.cpp24757 MVT RegVT = Op.getSimpleValueType(); in LowerLoad() local
24758 assert(RegVT.isVector() && "We only custom lower vector loads."); in LowerLoad()
24759 assert(RegVT.isInteger() && in LowerLoad()
24766 if (RegVT.getVectorElementType() == MVT::i1) { in LowerLoad()
24767 assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load"); in LowerLoad()
24768 assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT"); in LowerLoad()
24780 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, in LowerLoad()
51142 EVT RegVT = Ld->getValueType(0); in combineConstantPoolLoads() local
51150 if (!(RegVT.is128BitVector() || RegVT.is256BitVector())) in combineConstantPoolLoads()
51178 RegVT.getFixedSizeInBits()) { in combineConstantPoolLoads()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp249 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
251 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
256 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp351 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
352 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
358 RegVT.print(OS); in LowerFormalArguments()
367 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
372 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
375 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h217 MVT RegVT;
231 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
213 MVT RegVT; global() member
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp523 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
533 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
231 if (RegVT == MVT::i32) in LowerFormalArguments()
239 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Register, RegVT); in LowerFormalArguments()
251 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1393 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1395 if (RegVT == MVT::i8) { in LowerFormalArguments()
1397 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1404 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1421 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1426 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1526 EVT RegVT = VA.getLocVT(); in LowerCall() local
1536 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1539 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1542 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
458 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
462 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
468 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
482 << RegVT << "\n"); in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp643 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
644 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
649 << RegVT << "\n"; in LowerCCCArguments()
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp646 EVT RegVT = VA.getLocVT(); in LowerCall() local
657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
666 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
947 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
949 if (RegVT == MVT::i32) in LowerFormalArguments()
955 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
961 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
964 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp857 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
859 RegVT = VA.getValVT(); in LowerFormalArguments()
861 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
863 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
869 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
870 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
871 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
872 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
876 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
878 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1208 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1209 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1214 << RegVT << "\n"; in LowerCCCArguments()
1221 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3229 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
3230 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
3268 MVT VT = BB.RegVT; in visitBitTestCase()
9626 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in getRegistersForValue() local
9628 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in getRegistersForValue()
9642 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in getRegistersForValue()
9648 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in getRegistersForValue()
9649 OpInfo.ConstraintVT = RegVT; in getRegistersForValue()
9653 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in getRegistersForValue()
9670 ValueVT = RegVT; in getRegistersForValue()
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H A DTargetLowering.cpp9721 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
9722 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
9819 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
9821 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
9825 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
9841 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), in expandUnalignedLoad()
9859 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
9967 MVT RegVT = getRegisterType( in expandUnalignedStore() local
9972 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
9976 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
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H A DLegalizeIntegerTypes.cpp1860 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1866 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1882 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1120 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local
1121 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
H A DIRTranslator.cpp1116 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader()
1148 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3705 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3707 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3712 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3719 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3720 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3721 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3723 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3729 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5657 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5661 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5667 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5669 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5674 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5676 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5709 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5732 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5735 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff); in buildCallOperands()
5742 RegVT)); in buildCallOperands()
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H A DPPCISelDAGToDAG.cpp783 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
790 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
794 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
798 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
831 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
838 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
842 if (RegVT == MVT::i32) in tryTLSXFormLoad()
849 if (RegVT == MVT::i32) in tryTLSXFormLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3113 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
3118 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) { in IsEligibleForTailCallOptimization()
3127 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
4560 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4589 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
4591 else if (RegVT == MVT::f32) in LowerFormalArguments()
4593 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments()
4594 RegVT == MVT::v4bf16) in LowerFormalArguments()
4596 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments()
4597 RegVT == MVT::v8bf16) in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7349 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
7352 if (RegVT == MVT::i32) in LowerFormalArguments()
7354 else if (RegVT == MVT::i64) in LowerFormalArguments()
7356 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
7358 else if (RegVT == MVT::f32) in LowerFormalArguments()
7360 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
7362 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
7364 else if (RegVT.isScalableVector() && in LowerFormalArguments()
7365 RegVT.getVectorElementType() == MVT::i1) { in LowerFormalArguments()
7368 } else if (RegVT == MVT::aarch64svcount) { in LowerFormalArguments()
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