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Searched refs:RegVT (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1749 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1761 if (RegVT == MVT::i8) in LowerFormalArguments()
1763 else if (RegVT == MVT::i16) in LowerFormalArguments()
1765 else if (RegVT == MVT::i32) in LowerFormalArguments()
1767 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
1769 else if (RegVT == MVT::f16) in LowerFormalArguments()
1771 else if (RegVT == MVT::f32) in LowerFormalArguments()
1773 else if (RegVT == MVT::f64) in LowerFormalArguments()
1775 else if (RegVT == MVT::f80) in LowerFormalArguments()
1777 else if (RegVT == MVT::f128) in LowerFormalArguments()
[all …]
H A DX86ISelLowering.cpp25608 MVT RegVT = Op.getSimpleValueType(); in LowerLoad() local
25609 assert(RegVT.isVector() && "We only custom lower vector loads."); in LowerLoad()
25610 assert(RegVT.isInteger() && in LowerLoad()
25617 if (RegVT.getVectorElementType() == MVT::i1) { in LowerLoad()
25618 assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load"); in LowerLoad()
25619 assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT"); in LowerLoad()
25631 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, in LowerLoad()
52854 EVT RegVT = Ld->getValueType(0); in combineConstantPoolLoads() local
52862 if (!(RegVT.is128BitVector() || RegVT.is256BitVector())) in combineConstantPoolLoads()
52890 RegVT.getFixedSizeInBits()) { in combineConstantPoolLoads()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp249 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
251 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
256 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h222 MVT RegVT; member
236 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp367 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
368 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
374 RegVT.print(OS); in LowerFormalArguments()
383 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
388 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
391 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp506 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
507 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
510 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
516 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1346 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1348 if (RegVT == MVT::i8) { in LowerFormalArguments()
1350 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1357 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1374 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1379 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1479 EVT RegVT = VA.getLocVT(); in LowerCall() local
1489 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1492 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1495 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp522 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
523 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
528 << RegVT << "\n"; in LowerCCCArguments()
535 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
541 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
544 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp447 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
448 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
452 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
461 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
472 << RegVT << "\n"); in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp648 EVT RegVT = VA.getLocVT(); in LowerCall() local
659 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
662 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
665 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
668 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
948 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
950 if (RegVT == MVT::i32) in LowerFormalArguments()
956 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
962 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
965 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp926 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
928 RegVT = VA.getValVT(); in LowerFormalArguments()
930 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
932 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
938 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
939 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
940 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
941 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
945 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
947 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp449 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
451 if (RegVT != MVT::i32) in LowerFormalArguments()
468 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
480 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1179 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1180 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1185 << RegVT << "\n"; in LowerCCCArguments()
1192 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp184 const MVT RegVT = Subtarget.getScalarIntVT(); in PPCTargetLowering() local
200 setOperationAction(ISD::UADDO, RegVT, Custom); in PPCTargetLowering()
201 setOperationAction(ISD::USUBO, RegVT, Custom); in PPCTargetLowering()
204 setOperationAction(ISD::UADDO_CARRY, RegVT, Custom); in PPCTargetLowering()
205 setOperationAction(ISD::USUBO_CARRY, RegVT, Custom); in PPCTargetLowering()
280 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
282 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
285 AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
287 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
290 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, RegVT); in PPCTargetLowering()
[all …]
H A DPPCISelDAGToDAG.cpp783 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
790 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
794 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
798 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
831 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
838 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
842 if (RegVT == MVT::i32) in tryTLSXFormLoad()
849 if (RegVT == MVT::i32) in tryTLSXFormLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3254 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
3255 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
3292 MVT VT = BB.RegVT; in visitBitTestCase()
9789 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in getRegistersForValue() local
9791 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) { in getRegistersForValue()
9805 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in getRegistersForValue()
9811 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in getRegistersForValue()
9812 OpInfo.ConstraintVT = RegVT; in getRegistersForValue()
9816 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in getRegistersForValue()
9833 ValueVT = RegVT; in getRegistersForValue()
[all …]
H A DTargetLowering.cpp10215 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
10216 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
10311 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
10313 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
10317 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
10333 RegVT, dl, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), in expandUnalignedLoad()
10350 ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
10457 MVT RegVT = getRegisterType( in expandUnalignedStore() local
10462 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
10466 SDValue StackPtr = DAG.CreateStackTemporary(StoreMemVT, RegVT); in expandUnalignedStore()
[all …]
H A DLegalizeIntegerTypes.cpp1905 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
1911 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1927 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1119 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT); in getReturnInfo() local
1120 Type *PartTy = EVT(RegVT).getTypeForEVT(Context); in getReturnInfo()
H A DIRTranslator.cpp1130 B.RegVT = getMVTForLLT(MaskTy); in emitBitTestHeader()
1162 LLT SwitchTy = getLLTForMVT(BB.RegVT); in emitBitTestCase()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3863 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3865 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3870 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3877 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3878 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3879 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3881 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3887 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp7828 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
7831 if (RegVT == MVT::i32) in LowerFormalArguments()
7833 else if (RegVT == MVT::i64) in LowerFormalArguments()
7835 else if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
7837 else if (RegVT == MVT::f32) in LowerFormalArguments()
7839 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
7841 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
7843 else if (RegVT.isScalableVector() && in LowerFormalArguments()
7844 RegVT.getVectorElementType() == MVT::i1) { in LowerFormalArguments()
7847 } else if (RegVT == MVT::aarch64svcount) { in LowerFormalArguments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5021 EVT RegVT = Op.getValueType(); in lowerATOMIC_LOAD() local
5022 if (RegVT.getSizeInBits() == 128) in lowerATOMIC_LOAD()
6913 EVT RegVT = Op.getValueType(); in lowerLoadF16() local
6914 assert(RegVT == MVT::f16 && "Expected to lower an f16 load."); in lowerLoadF16()
6915 (void)RegVT; in lowerLoadF16()
6921 assert(EVT(RegVT) == AtomicLd->getMemoryVT() && "Unhandled f16 load"); in lowerLoadF16()
6927 assert(EVT(RegVT) == Ld->getMemoryVT() && "Unhandled f16 load"); in lowerLoadF16()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4630 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
4659 if (RegVT == MVT::f16 || RegVT == MVT::bf16) in LowerFormalArguments()
4661 else if (RegVT == MVT::f32) in LowerFormalArguments()
4663 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 || in LowerFormalArguments()
4664 RegVT == MVT::v4bf16) in LowerFormalArguments()
4666 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 || in LowerFormalArguments()
4667 RegVT == MVT::v8bf16) in LowerFormalArguments()
4669 else if (RegVT == MVT::i32) in LowerFormalArguments()
4677 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
4710 RegVT.isScalarInteger() && Arg.ArgVT.bitsLT(MVT::i32)) in LowerFormalArguments()