1718       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()  local
1730         if (RegVT == MVT::i8)  in LowerFormalArguments()
1732         else if (RegVT == MVT::i16)  in LowerFormalArguments()
1734         else if (RegVT == MVT::i32)  in LowerFormalArguments()
1736         else if (Is64Bit && RegVT == MVT::i64)  in LowerFormalArguments()
1738         else if (RegVT == MVT::f16)  in LowerFormalArguments()
1740         else if (RegVT == MVT::f32)  in LowerFormalArguments()
1742         else if (RegVT == MVT::f64)  in LowerFormalArguments()
1744         else if (RegVT == MVT::f80)  in LowerFormalArguments()
1746         else if (RegVT == MVT::f128)  in LowerFormalArguments()
1748         else if (RegVT.is512BitVector())  in LowerFormalArguments()
1750         else if (RegVT.is256BitVector())  in LowerFormalArguments()
1752         else if (RegVT.is128BitVector())  in LowerFormalArguments()
1754         else if (RegVT == MVT::x86mmx)  in LowerFormalArguments()
1756         else if (RegVT == MVT::v1i1)  in LowerFormalArguments()
1758         else if (RegVT == MVT::v8i1)  in LowerFormalArguments()
1760         else if (RegVT == MVT::v16i1)  in LowerFormalArguments()
1762         else if (RegVT == MVT::v32i1)  in LowerFormalArguments()
1764         else if (RegVT == MVT::v64i1)  in LowerFormalArguments()
1770         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);  in LowerFormalArguments()
1777         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,  in LowerFormalArguments()
1780         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,  in LowerFormalArguments()
1787         if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)  in LowerFormalArguments()
1794           ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG);  in LowerFormalArguments()
2162     EVT RegVT = VA.getLocVT();  in LowerCall()  local
2171       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);  in LowerCall()
2174       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);  in LowerCall()
2179         Arg = lowerMasksToReg(Arg, RegVT, dl, DAG);  in LowerCall()
2180       else if (RegVT.is128BitVector()) {  in LowerCall()
2186         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);  in LowerCall()
2189       Arg = DAG.getBitcast(RegVT, Arg);  in LowerCall()