Lines Matching refs:RegVT
1393 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1395 if (RegVT == MVT::i8) { in LowerFormalArguments()
1397 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1404 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1421 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1426 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1526 EVT RegVT = VA.getLocVT(); in LowerCall() local
1536 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1539 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1542 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1545 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()