24757   MVT RegVT = Op.getSimpleValueType();  in LowerLoad()  local
24758   assert(RegVT.isVector() && "We only custom lower vector loads.");  in LowerLoad()
24759   assert(RegVT.isInteger() &&  in LowerLoad()
24766   if (RegVT.getVectorElementType() == MVT::i1) {  in LowerLoad()
24767     assert(EVT(RegVT) == Ld->getMemoryVT() && "Expected non-extending load");  in LowerLoad()
24768     assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT");  in LowerLoad()
24780     Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT,  in LowerLoad()
51142   EVT RegVT = Ld->getValueType(0);  in combineConstantPoolLoads()  local
51150   if (!(RegVT.is128BitVector() || RegVT.is256BitVector()))  in combineConstantPoolLoads()
51178             RegVT.getFixedSizeInBits()) {  in combineConstantPoolLoads()
51191           unsigned NumBits = std::min(RegVT.getScalarSizeInBits(),  in combineConstantPoolLoads()
51199                   SDValue(User, 0), 0, DAG, SDLoc(N), RegVT.getSizeInBits());  in combineConstantPoolLoads()
51200               Extract = DAG.getBitcast(RegVT, Extract);  in combineConstantPoolLoads()
51216   EVT RegVT = Ld->getValueType(0);  in combineLoad()  local
51226   if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&  in combineLoad()
51230        (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,  in combineLoad()
51233     unsigned NumElems = RegVT.getVectorNumElements();  in combineLoad()
51254     SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);  in combineLoad()
51260   if (Ext == ISD::NON_EXTLOAD && !Subtarget.hasAVX512() && RegVT.isVector() &&  in combineLoad()
51261       RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) {  in combineLoad()
51262     unsigned NumElts = RegVT.getVectorNumElements();  in combineLoad()
51269       SDValue BoolVec = DAG.getBitcast(RegVT, IntLoad);  in combineLoad()
51277       (RegVT.is128BitVector() || RegVT.is256BitVector())) {  in combineLoad()
51288               RegVT.getFixedSizeInBits()) {  in combineLoad()
51290                                            RegVT.getSizeInBits());  in combineLoad()
51291         Extract = DAG.getBitcast(RegVT, Extract);  in combineLoad()
51308       return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,  in combineLoad()