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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp422 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1,
430 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
438 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
447 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
449 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
460 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
462 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
577 SDValue N0,
579 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
[all …]
H A DTargetLowering.cpp779 SDValue N0 = Op.getOperand(0); in SimplifyMultipleUseDemandedBits() local
780 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts, in SimplifyMultipleUseDemandedBits()
782 return N0; in SimplifyMultipleUseDemandedBits()
3370 SDValue N0 = Op.getOperand(0); in SimplifyDemandedVectorElts() local
3371 if (TLO.DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts, in SimplifyDemandedVectorElts()
3373 return TLO.CombineTo(Op, N0); in SimplifyDemandedVectorElts()
3377 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1) in SimplifyDemandedVectorElts()
3380 TLO.DAG.getFreeze(N0.getOperand(0)))); in SimplifyDemandedVectorElts()
3993 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, in buildLegalVectorShuffle() argument
3998 std::swap(N0, N1); in buildLegalVectorShuffle()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelDAGToDAG.cpp148 SDValue N0 = Node->getOperand(0); in Select() local
156 CurDAG->getMachineNode(Xtensa::SLL, DL, VT, N0, SDValue(SSL, 0)); in Select()
163 SDValue N0 = Node->getOperand(0); in Select() local
174 Xtensa::EXTUI, DL, VT, N0, CurDAG->getTargetConstant(ShAmt, DL, VT), in Select()
182 CurDAG->getMachineNode(Xtensa::SRL, DL, VT, N0, SDValue(SSR, 0)); in Select()
187 SDValue N0 = Node->getOperand(0); in Select() local
195 CurDAG->getMachineNode(Xtensa::SRA, DL, VT, N0, SDValue(SSR, 0)); in Select()
202 SDValue N0 = Node->getOperand(0); in Select() local
207 CurDAG->getMachineNode(Xtensa::SRC, DL, VT, N0, N1, SDValue(SSL, 0)); in Select()
212 SDValue N0 = Node->getOperand(0); in Select() local
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/freebsd/crypto/openssl/crypto/bn/asm/
H A Darmv4-mont.pl302 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
351 vld1.32 {$N0-$N3}, [$nptr]!
357 vmlal.u32 @ACC[0],$Ni,${N0}[0]
359 vmlal.u32 @ACC[1],$Ni,${N0}[1]
406 vmlal.u32 @ACC[0],$Ni,${N0}[0]
407 vmlal.u32 @ACC[1],$Ni,${N0}[1]
479 vld1.32 {$N0-$N3},[$nptr]!
499 vmlal.u32 @ACC[0],$Ni,${N0}[0]
501 vmlal.u32 @ACC[1],$Ni,${N0}[1]
536 vmlal.u32 @ACC[0],$Ni,${N0}[0]
[all …]
H A Dppc64-mont.pl176 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
398 lfd $N0,`$FRAME+96`($sp)
406 fcfid $N0,$N0
423 stfd $N0,40($nap_d) ; save n[j] in double format
445 fmadd $T0a,$N0,$na,$T0a
446 fmadd $T0b,$N0,$nb,$T0b
448 fmadd $T1a,$N0,$nc,$T1a
449 fmadd $T1b,$N0,$nd,$T1b
536 lfd $N0,`$FRAME+96`($sp)
544 fcfid $N0,$N0
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H A Darmv8-mont.pl299 my ($A0,$A1,$N0,$N1)=map("v$_",(0..3));
364 ld1 {$N0.4s,$N1.4s},[$nptr],#32
384 umlal @ACC[0].2d,$Ni.2s,$N0.s[0]
385 umlal @ACC[1].2d,$Ni.2s,$N0.s[1]
387 umlal @ACC[2].2d,$Ni.2s,$N0.s[2]
389 umlal @ACC[3].2d,$Ni.2s,$N0.s[3]
422 umlal @ACC[0].2d,$Ni.2s,$N0.s[0]
424 umlal @ACC[1].2d,$Ni.2s,$N0.s[1]
425 umlal @ACC[2].2d,$Ni.2s,$N0.s[2]
429 umlal @ACC[3].2d,$Ni.2s,$N0.s[3]
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp527 SDValue N0 = Node->getOperand(0); in tryShrinkShlLogicImm() local
540 SDValue Shift = N0; in tryShrinkShlLogicImm()
546 if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in tryShrinkShlLogicImm()
547 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
549 Shift = N0.getOperand(0); in tryShrinkShlLogicImm()
613 SDValue N0 = Node->getOperand(0); in trySignedBitfieldExtract() local
614 if (!N0.hasOneUse()) in trySignedBitfieldExtract()
617 auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, in trySignedBitfieldExtract()
625 return CurDAG->getMachineNode(Opc, DL, VT, N0.getOperand(0), in trySignedBitfieldExtract()
636 if (N0.getOpcode() == ISD::SHL) { in trySignedBitfieldExtract()
[all …]
H A DRISCVISelLowering.cpp15051 SDValue N0 = N->getOperand(0); in transformAddShlImm() local
15053 if (N0->getOpcode() != ISD::SHL || N1->getOpcode() != ISD::SHL || in transformAddShlImm()
15054 !N0->hasOneUse() || !N1->hasOneUse()) in transformAddShlImm()
15058 auto *N0C = dyn_cast<ConstantSDNode>(N0->getOperand(1)); in transformAddShlImm()
15083 SDValue NS = (C0 < C1) ? N0->getOperand(0) : N1->getOperand(0); in transformAddShlImm()
15084 SDValue NL = (C0 > C1) ? N0->getOperand(0) : N1->getOperand(0); in transformAddShlImm()
15231 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
15233 if (SDValue Result = combineSelectAndUse(N, N0, N1, DAG, AllOnes, Subtarget)) in combineSelectAndUseCommutative()
15235 if (SDValue Result = combineSelectAndUse(N, N1, N0, DAG, AllOnes, Subtarget)) in combineSelectAndUseCommutative()
15265 SDValue N0 = N->getOperand(0); in transformAddImmMulImm() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp579 SDValue N0 = N.getOperand(0); in matchWrapper() local
590 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
597 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
605 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
608 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) { in matchWrapper()
610 } else if (auto *J = dyn_cast<JumpTableSDNode>(N0)) { in matchWrapper()
613 } else if (auto *BA = dyn_cast<BlockAddressSDNode>(N0)) { in matchWrapper()
633 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
637 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
642 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1556 SDValue N0 = N->getOperand(0); in tryOptimizeRem8Extend() local
1559 if (!N0.isMachineOpcode() || in tryOptimizeRem8Extend()
1560 N0.getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG || in tryOptimizeRem8Extend()
1561 N0.getConstantOperandVal(1) != X86::sub_8bit) in tryOptimizeRem8Extend()
1567 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend()
1944 SDValue N0 = N.getOperand(0); in matchWrapper() local
1945 if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) { in matchWrapper()
1949 } else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in matchWrapper()
1954 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in matchWrapper()
1957 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) { in matchWrapper()
[all …]
H A DX86ISelLowering.cpp6136 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
6140 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits, in getFauxShuffleMask()
6153 Ops.push_back(IsAndN ? N1 : N0); in getFauxShuffleMask()
6159 SDValue N0 = peekThroughBitcasts(N.getOperand(0)); in getFauxShuffleMask() local
6161 if (!N0.getValueType().isVector() || !N1.getValueType().isVector()) in getFauxShuffleMask()
6166 APInt Demand0 = APInt::getAllOnes(N0.getValueType().getVectorNumElements()); in getFauxShuffleMask()
6168 if (!getTargetShuffleInputs(N0, Demand0, SrcInputs0, SrcMask0, DAG, in getFauxShuffleMask()
6402 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
6404 assert(N0.getValueType().getVectorNumElements() == (NumElts / 2) && in getFauxShuffleMask()
6415 if ((!(N0.isUndef() || EltsLHS.isZero()) && in getFauxShuffleMask()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3581 SDValue N0 = Op.getOperand(0); in LowerFP_TO_FP16() local
3584 if (N0.getValueType() == MVT::f32) in LowerFP_TO_FP16()
3585 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
3592 return LowerF64ToF16Safe(N0, DL, DAG); in LowerFP_TO_FP16()
3978 SDValue N0 = N->getOperand(0); in performAssertSZExtCombine() local
3982 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
3987 SDValue Src = N0.getOperand(0); in performAssertSZExtCombine()
4463 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
4466 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4472 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
[all …]
H A DAMDGPUISelDAGToDAG.cpp848 SDValue &N0, SDValue &N1) { in getBaseWithOffsetUsingSplitOR() argument
869 N0 = BaseLo.getOperand(0).getOperand(0); in getBaseWithOffsetUsingSplitOR()
1198 SDValue N0 = Addr.getOperand(0); in SelectDS1Addr1Offset() local
1201 if (isDSOffsetLegal(N0, C1->getSExtValue())) { in SelectDS1Addr1Offset()
1203 Base = N0; in SelectDS1Addr1Offset()
1377 SDValue N0 = Addr.getOperand(0); in SelectDSReadWrite2() local
1384 if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) { in SelectDSReadWrite2()
1385 Base = N0; in SelectDSReadWrite2()
1472 SDValue N0 = Addr; in SelectMUBUF() local
1476 N0 = Addr.getOperand(0); in SelectMUBUF()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp147 SDValue N0 = N.getOperand(0); in MatchWrapper() local
149 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { in MatchWrapper()
153 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { in MatchWrapper()
158 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { in MatchWrapper()
161 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { in MatchWrapper()
165 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); in MatchWrapper()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9659 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
9661 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9662 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9670 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
9672 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9673 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9684 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
9688 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
9693 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9700 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/
H A DScheduler.cpp208 auto *N0 = DAG.getNode(Instrs[0]); in getBndlSchedState() local
209 auto *SB0 = N0 != nullptr ? N0->getSchedBundle() : nullptr; in getBndlSchedState()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h2104 LLVM_ABI OverflowKind computeOverflowForSignedAdd(SDValue N0,
2108 LLVM_ABI OverflowKind computeOverflowForUnsignedAdd(SDValue N0,
2112 OverflowKind computeOverflowForAdd(bool IsSigned, SDValue N0,
2114 return IsSigned ? computeOverflowForSignedAdd(N0, N1)
2115 : computeOverflowForUnsignedAdd(N0, N1);
2119 bool willNotOverflowAdd(bool IsSigned, SDValue N0, SDValue N1) const {
2120 return computeOverflowForAdd(IsSigned, N0, N1) == OFK_Never;
2124 LLVM_ABI OverflowKind computeOverflowForSignedSub(SDValue N0,
2128 LLVM_ABI OverflowKind computeOverflowForUnsignedSub(SDValue N0,
2132 OverflowKind computeOverflowForSub(bool IsSigned, SDValue N0,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp548 SDValue N0 = Op.getOperand(0); in isADDADDMUL() local
552 if (N0.getOpcode() == ISD::ADD) { in isADDADDMUL()
553 AddOp = N0; in isADDADDMUL()
557 OtherOp = N0; in isADDADDMUL()
1508 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); in PerformDAGCombine()
1513 EVT VT = N0.getValueType(); in PerformDAGCombine()
1517 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1536 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); in PerformDAGCombine()
1544 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
[all …]
/freebsd/crypto/openssl/test/recipes/15-test_dsaparam_data/valid/
H A Dp3072_q256_t1862_gind1.pem10 nDOvJUDt2WSnAiEAtxINd2uhphWpMhicTM/N0/aVpQ7yv2rVTRCdGK48XzkCggGA
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5228 SDValue N0 = N.getOperand(0); in isAddSubSExt() local
5230 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
5231 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
5239 SDValue N0 = N.getOperand(0); in isAddSubZExt() local
5241 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
5242 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
5373 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG, in selectUmullSmull() argument
5375 bool IsN0SExt = isSignExtended(N0, DAG); in selectUmullSmull()
5380 bool IsN0ZExt = isZeroExtended(N0, DAG); in selectUmullSmull()
5387 EVT VT = N0.getValueType(); in selectUmullSmull()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4841 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
4843 EVT VT = N0.getValueType(); in PerformADDCombineWithOperands()
4849 if (!N0.getNode()->hasOneUse()) in PerformADDCombineWithOperands()
4855 if (N0.getOpcode() == ISD::SELECT) { in PerformADDCombineWithOperands()
4857 if (isConstZero(N0->getOperand(1))) in PerformADDCombineWithOperands()
4859 else if (isConstZero(N0->getOperand(2))) in PerformADDCombineWithOperands()
4864 SDValue M = N0->getOperand((ZeroOpNum == 1) ? 2 : 1); in PerformADDCombineWithOperands()
4872 return DCI.DAG.getSelect(SDLoc(N), VT, N0->getOperand(0), in PerformADDCombineWithOperands()
4881 PerformFADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformFADDCombineWithOperands() argument
4884 EVT VT = N0.getValueType(); in PerformFADDCombineWithOperands()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-qcom-dc-scm-v1.dts108 /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
/freebsd/contrib/pam_modules/pam_passwdqc/
H A DREADME21 min=N0,N1,N2,N3,N4 [min=disabled,24,12,8,7]
28 N0 is used for passwords consisting of characters from one character
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7683 SDValue N0 = N->getOperand(0); in combineZERO_EXTEND() local
7685 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) { in combineZERO_EXTEND()
7686 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0)); in combineZERO_EXTEND()
7687 auto *FalseOp = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in combineZERO_EXTEND()
7689 SDLoc DL(N0); in combineZERO_EXTEND()
7692 N0.getOperand(2), N0.getOperand(3), N0.getOperand(4) }; in combineZERO_EXTEND()
7695 if (!N0.hasOneUse()) { in combineZERO_EXTEND()
7697 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), NewSelect); in combineZERO_EXTEND()
7698 DCI.CombineTo(N0.getNode(), TruncSelect); in combineZERO_EXTEND()
7706 if (N0.getOpcode() == ISD::XOR && in combineZERO_EXTEND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1399 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
1401 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1402 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
1405 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
1413 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
1418 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)) in PerformSUBCombine()

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