Lines Matching refs:N0
5070 SDValue N0 = N.getOperand(0); in isAddSubSExt() local
5072 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
5073 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
5081 SDValue N0 = N.getOperand(0); in isAddSubZExt() local
5083 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
5084 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
5215 static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG, in selectUmullSmull() argument
5217 bool IsN0SExt = isSignExtended(N0, DAG); in selectUmullSmull()
5222 bool IsN0ZExt = isZeroExtended(N0, DAG); in selectUmullSmull()
5230 !isExtendedBUILD_VECTOR(N0, DAG, false) && in selectUmullSmull()
5234 ZextOperand = N0.getOperand(0); in selectUmullSmull()
5239 DAG.getSExtOrTrunc(ZextOperand, DL, N0.getValueType()); in selectUmullSmull()
5241 N0 = NewSext; in selectUmullSmull()
5250 EVT VT = N0.getValueType(); in selectUmullSmull()
5253 if (DAG.MaskedValueIsZero(IsN0ZExt ? N1 : N0, Mask)) in selectUmullSmull()
5262 if (IsN1SExt && isAddSubSExt(N0, DAG)) { in selectUmullSmull()
5266 if (IsN1ZExt && isAddSubZExt(N0, DAG)) { in selectUmullSmull()
5271 std::swap(N0, N1); in selectUmullSmull()
5289 SDValue N0 = Op.getOperand(0); in LowerMUL() local
5294 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
5295 isNullConstant(N0.getOperand(1)) && in LowerMUL()
5298 N0 = N0.getOperand(0); in LowerMUL()
5300 VT = N0.getValueType(); in LowerMUL()
5314 unsigned NewOpc = selectUmullSmull(N0, N1, DAG, DL, isMLA); in LowerMUL()
5333 Op0 = skipExtensionForVectorMULL(N0, DAG); in LowerMUL()
5344 SDValue N00 = skipExtensionForVectorMULL(N0.getOperand(0), DAG); in LowerMUL()
5345 SDValue N01 = skipExtensionForVectorMULL(N0.getOperand(1), DAG); in LowerMUL()
5349 DAG.getNode(N0.getOpcode(), DL, VT, in LowerMUL()
7159 bool AArch64TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0, in isReassocProfitable() argument
7161 if (!N0.hasOneUse()) in isReassocProfitable()
7170 return N0.getOpcode() != ISD::ADD; in isReassocProfitable()
14090 SDValue N0 = N->getOperand(0); in LowerBUILD_VECTOR() local
14094 Vector = N0.getNode(); in LowerBUILD_VECTOR()
14098 N0.getValueType().getVectorElementType()) in LowerBUILD_VECTOR()
14100 } else if (Vector != N0.getNode()) { in LowerBUILD_VECTOR()
17991 SDValue N0 = N->getOperand(0); in BuildSREMPow2() local
17996 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETGE, CCVal, DAG, DL); in BuildSREMPow2()
17997 SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, Pow2MinusOne); in BuildSREMPow2()
18006 SDValue Negs = DAG.getNode(AArch64ISD::SUBS, DL, VTs, Zero, N0); in BuildSREMPow2()
18007 SDValue AndPos = DAG.getNode(ISD::AND, DL, VT, N0, Pow2MinusOne); in BuildSREMPow2()
18221 SDValue N0 = N->getOperand(0).getOperand(0); in performVectorExtCombine() local
18223 EVT InVT = N0.getValueType(); in performVectorExtCombine()
18233 SDValue NewN0 = DAG.getNode(N->getOperand(0).getOpcode(), DL, HalfVT, N0); in performVectorExtCombine()
18262 SDValue N0 = N->getOperand(0); in performMulCombine() local
18280 if (IsAddSubWith1(N0)) { in performMulCombine()
18286 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMulCombine()
18287 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
18299 if (IsSVECntIntrinsic(N0) || in performMulCombine()
18300 (N0->getOpcode() == ISD::TRUNCATE && in performMulCombine()
18301 (IsSVECntIntrinsic(N0->getOperand(0))))) in performMulCombine()
18321 if (N0->hasOneUse() && (isSignExtended(N0, DAG) || in performMulCombine()
18322 isZeroExtended(N0, DAG))) in performMulCombine()
18335 auto Shl = [&](SDValue N0, unsigned N1) { in performMulCombine() argument
18336 if (!N0.getNode()) in performMulCombine()
18339 if (N1 >= N0.getValueSizeInBits()) in performMulCombine()
18342 return DAG.getNode(ISD::SHL, DL, VT, N0, RHS); in performMulCombine()
18344 auto Add = [&](SDValue N0, SDValue N1) { in performMulCombine() argument
18345 if (!N0.getNode() || !N1.getNode()) in performMulCombine()
18347 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); in performMulCombine()
18349 auto Sub = [&](SDValue N0, SDValue N1) { in performMulCombine() argument
18350 if (!N0.getNode() || !N1.getNode()) in performMulCombine()
18352 return DAG.getNode(ISD::SUB, DL, VT, N0, N1); in performMulCombine()
18355 if (!N0.getNode()) in performMulCombine()
18430 return Shl(Add(Shl(N0, ShiftAmt), N0), TrailingZeroes); in performMulCombine()
18433 return Sub(Shl(N0, ShiftAmt), N0); in performMulCombine()
18436 return Sub(Shl(N0, ShiftAmt), Shl(N0, TrailingZeroes)); in performMulCombine()
18446 SDValue MVal = Add(Shl(N0, ShiftM1), N0); in performMulCombine()
18456 SDValue MVal = Add(Shl(N0, CVM.getZExtValue()), N0); in performMulCombine()
18457 return Add(Shl(MVal, CVN.getZExtValue()), N0); in performMulCombine()
18467 SDValue MVal = Sub(N0, Shl(N0, CVM.getZExtValue())); in performMulCombine()
18468 return Sub(N0, Shl(MVal, CVN.getZExtValue())); in performMulCombine()
18480 return Sub(N0, Shl(N0, ShiftAmt)); in performMulCombine()
18483 return Negate(Add(Shl(N0, ShiftAmt), N0)); in performMulCombine()
18486 return Sub(Shl(N0, TrailingZeroes), Shl(N0, ShiftAmt)); in performMulCombine()
18557 SDValue N0 = N->getOperand(0); in performIntToFpCombine() local
18558 if (Subtarget->isNeonAvailable() && ISD::isNormalLoad(N0.getNode()) && in performIntToFpCombine()
18559 N0.hasOneUse() && in performIntToFpCombine()
18561 !cast<LoadSDNode>(N0)->isVolatile()) { in performIntToFpCombine()
18562 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in performIntToFpCombine()
18667 SDValue N0 = N->getOperand(0); in tryCombineToBSL() local
18668 if (N0.getOpcode() != ISD::AND) in tryCombineToBSL()
18680 SDValue O0 = N0->getOperand(i); in tryCombineToBSL()
18688 SubSibling = N0->getOperand(1 - i); in tryCombineToBSL()
18693 AddSibling = N0->getOperand(1 - i); in tryCombineToBSL()
18721 if (ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) && in tryCombineToBSL()
18724 return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i), in tryCombineToBSL()
18725 N0->getOperand(1 - i), N1->getOperand(1 - j)); in tryCombineToBSL()
18727 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i)); in tryCombineToBSL()
18743 return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i), in tryCombineToBSL()
18744 N0->getOperand(1 - i), N1->getOperand(1 - j)); in tryCombineToBSL()
19179 SDValue N0 = N->getOperand(0); in performFirstTrueTestVectorCombine() local
19180 EVT VT = N0.getValueType(); in performFirstTrueTestVectorCombine()
19188 if (!isPredicateCCSettingOp(N0)) in performFirstTrueTestVectorCombine()
19194 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::FIRST_ACTIVE); in performFirstTrueTestVectorCombine()
19209 SDValue N0 = N->getOperand(0); in performLastTrueTestVectorCombine() local
19210 EVT OpVT = N0.getValueType(); in performLastTrueTestVectorCombine()
19231 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE); in performLastTrueTestVectorCombine()
19244 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in performExtractVectorEltCombine() local
19248 bool IsStrict = N0->isStrictFPOpcode(); in performExtractVectorEltCombine()
19251 if (N0.getOpcode() == AArch64ISD::DUP) in performExtractVectorEltCombine()
19252 return VT.isInteger() ? DAG.getZExtOrTrunc(N0.getOperand(0), SDLoc(N), VT) in performExtractVectorEltCombine()
19253 : N0.getOperand(0); in performExtractVectorEltCombine()
19264 if (isNullConstant(N1) && hasPairwiseAdd(N0->getOpcode(), VT, FullFP16) && in performExtractVectorEltCombine()
19265 (!IsStrict || N0.hasOneUse())) { in performExtractVectorEltCombine()
19266 SDLoc DL(N0); in performExtractVectorEltCombine()
19267 SDValue N00 = N0->getOperand(IsStrict ? 1 : 0); in performExtractVectorEltCombine()
19268 SDValue N01 = N0->getOperand(IsStrict ? 2 : 1); in performExtractVectorEltCombine()
19286 return DAG.getNode(N0->getOpcode(), DL, VT, Extract1, Extract2); in performExtractVectorEltCombine()
19292 SDValue Ret = DAG.getNode(N0->getOpcode(), DL, in performExtractVectorEltCombine()
19294 {N0->getOperand(0), Extract1, Extract2}); in performExtractVectorEltCombine()
19296 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Ret.getValue(1)); in performExtractVectorEltCombine()
19309 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in performConcatVectorsCombine() local
19310 unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode(); in performConcatVectorsCombine()
19328 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine()
19394 N1Opc == ISD::TRUNCATE && N->isOnlyUserOf(N0.getNode()) && in performConcatVectorsCombine()
19400 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine()
19402 if (isBitwiseVectorNegate(N00) && N0->isOnlyUserOf(N00.getNode()) && in performConcatVectorsCombine()
19407 DAG.getNode(ISD::TRUNCATE, dl, N0.getValueType(), in performConcatVectorsCombine()
19424 DAG.getTargetLoweringInfo().isBinOp(N0Opc) && N0->hasOneUse() && in performConcatVectorsCombine()
19426 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine()
19427 SDValue N01 = N0->getOperand(1); in performConcatVectorsCombine()
19465 if (N->getNumOperands() == 2 && IsRSHRN(N0) && in performConcatVectorsCombine()
19467 N0.getConstantOperandVal(1) == N1.getConstantOperandVal(1)) || in performConcatVectorsCombine()
19469 SDValue X = N0.getOperand(0).getOperand(0); in performConcatVectorsCombine()
19477 DAG.getConstant(1ULL << (N0.getConstantOperandVal(1) - 1), dl, BVT)); in performConcatVectorsCombine()
19479 DAG.getNode(AArch64ISD::VLSHR, dl, BVT, Add, N0.getOperand(1)); in performConcatVectorsCombine()
19485 N1Opc == AArch64ISD::ZIP2 && N0.getOperand(0) == N1.getOperand(0) && in performConcatVectorsCombine()
19486 N0.getOperand(1) == N1.getOperand(1)) { in performConcatVectorsCombine()
19487 SDValue E0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(0), in performConcatVectorsCombine()
19488 DAG.getUNDEF(N0.getValueType())); in performConcatVectorsCombine()
19489 SDValue E1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N0.getOperand(1), in performConcatVectorsCombine()
19490 DAG.getUNDEF(N0.getValueType())); in performConcatVectorsCombine()
19497 if (N->getNumOperands() == 2 && N0 == N1 && VT.getVectorNumElements() == 2) { in performConcatVectorsCombine()
19499 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG), in performConcatVectorsCombine()
19527 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0), in performConcatVectorsCombine()
20007 SDValue N0 = CSel.getOperand(0); in performNegCSelCombine() local
20012 if (!isNegatedInteger(N0) && !isNegatedInteger(N1)) in performNegCSelCombine()
20015 SDValue N0N = getNegatedInteger(N0, DAG); in performNegCSelCombine()
20281 SDValue N0 = N->getOperand(0); in performTruncateCombine() local
20282 if (VT.isFixedLengthVector() && VT.is64BitVector() && N0.hasOneUse() && in performTruncateCombine()
20283 N0.getOpcode() == AArch64ISD::DUP) { in performTruncateCombine()
20284 SDValue Op = N0.getOperand(0); in performTruncateCombine()
20286 N0.getOperand(0).getValueType().getScalarType() == MVT::i64) in performTruncateCombine()
20288 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Op); in performTruncateCombine()
24206 SDValue N0 = N->getOperand(0); in performVSelectCombine() local
24207 EVT CCVT = N0.getValueType(); in performVSelectCombine()
24209 if (isAllActivePredicate(DAG, N0)) in performVSelectCombine()
24212 if (isAllInactivePredicate(N0)) in performVSelectCombine()
24247 EVT CmpVT = N0.getOperand(0).getValueType(); in performVSelectCombine()
24248 if (N0.getOpcode() != ISD::SETCC || in performVSelectCombine()
24263 N0.getOperand(0), N0.getOperand(1), in performVSelectCombine()
24264 cast<CondCodeSDNode>(N0.getOperand(2))->get()); in performVSelectCombine()
24276 SDValue N0 = N->getOperand(0); in performSelectCombine() local
24279 if (N0.getOpcode() != ISD::SETCC) in performSelectCombine()
24288 assert((N0.getValueType() == MVT::i1 || N0.getValueType() == MVT::i32) && in performSelectCombine()
24294 EVT SrcVT = N0.getOperand(0).getValueType(); in performSelectCombine()
24322 SDLoc DL(N0); in performSelectCombine()
24324 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); in performSelectCombine()
24326 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); in performSelectCombine()
24327 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine()
24968 SDValue N0 = N->getOperand(0); in performFPExtendCombine() local
24983 if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) && in performFPExtendCombine()
24984 N0.hasOneUse() && Subtarget->useSVEForFixedLengthVectors() && in performFPExtendCombine()
24987 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in performFPExtendCombine()
24990 N0.getValueType(), LN0->getMemOperand()); in performFPExtendCombine()
24993 N0.getNode(), in performFPExtendCombine()
24994 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad, in performFPExtendCombine()
24995 DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)), in performFPExtendCombine()