Lines Matching refs:N0
5841 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
5845 if (!getTargetConstantBitsFromNode(IsAndN ? N0 : N1, 8, UndefElts, EltBits, in getFauxShuffleMask()
5858 Ops.push_back(IsAndN ? N1 : N0); in getFauxShuffleMask()
5864 SDValue N0 = peekThroughBitcasts(N.getOperand(0)); in getFauxShuffleMask() local
5866 if (!N0.getValueType().isVector() || !N1.getValueType().isVector()) in getFauxShuffleMask()
5871 APInt Demand0 = APInt::getAllOnes(N0.getValueType().getVectorNumElements()); in getFauxShuffleMask()
5873 if (!getTargetShuffleInputs(N0, Demand0, SrcInputs0, SrcMask0, DAG, in getFauxShuffleMask()
5897 Ops.push_back(N0); in getFauxShuffleMask()
6085 SDValue N0 = N.getOperand(0); in getFauxShuffleMask() local
6087 assert(N0.getValueType().getVectorNumElements() == (NumElts / 2) && in getFauxShuffleMask()
6098 if ((!(N0.isUndef() || EltsLHS.isZero()) && in getFauxShuffleMask()
6099 DAG.ComputeNumSignBits(N0, EltsLHS, Depth + 1) <= NumBitsPerElt) || in getFauxShuffleMask()
6106 if (N0.getOpcode() == X86ISD::VSRAI && N->isOnlyUserOf(N0.getNode()) && in getFauxShuffleMask()
6107 N0.getConstantOperandAPInt(1) == NumBitsPerElt) { in getFauxShuffleMask()
6109 N0 = N0.getOperand(0); in getFauxShuffleMask()
6118 if ((!(N0.isUndef() || EltsLHS.isZero()) && in getFauxShuffleMask()
6119 !DAG.MaskedValueIsZero(N0, ZeroMask, EltsLHS, Depth + 1)) || in getFauxShuffleMask()
6125 bool IsUnary = (N0 == N1); in getFauxShuffleMask()
6127 Ops.push_back(N0); in getFauxShuffleMask()
12431 static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0, in lowerShuffleOfExtractsAsVperm() argument
12434 MVT VT = N0.getSimpleValueType(); in lowerShuffleOfExtractsAsVperm()
12440 if (N0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
12442 N0.getOperand(0) != N1.getOperand(0) || in lowerShuffleOfExtractsAsVperm()
12443 !N0.hasOneUse() || !N1.hasOneUse()) in lowerShuffleOfExtractsAsVperm()
12446 SDValue WideVec = N0.getOperand(0); in lowerShuffleOfExtractsAsVperm()
12455 const APInt &ExtIndex0 = N0.getConstantOperandAPInt(1); in lowerShuffleOfExtractsAsVperm()
18213 SDValue N0 = Op.getOperand(0); in LowerINSERT_VECTOR_ELT() local
18221 DAG.getBitcast(IVT, N0), in LowerINSERT_VECTOR_ELT()
18250 return DAG.getSelectCC(dl, IdxSplat, Indices, EltSplat, N0, in LowerINSERT_VECTOR_ELT()
18272 return DAG.getNode(ISD::OR, dl, VT, N0, CstVector); in LowerINSERT_VECTOR_ELT()
18283 return DAG.getVectorShuffle(VT, dl, N0, CstVector, BlendMask); in LowerINSERT_VECTOR_ELT()
18299 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, in LowerINSERT_VECTOR_ELT()
18319 return DAG.getVectorShuffle(VT, dl, N0, N1SplatVec, BlendMask); in LowerINSERT_VECTOR_ELT()
18323 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
18333 return insert128BitVector(N0, V, IdxVal, DAG, dl); in LowerINSERT_VECTOR_ELT()
18338 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(N0.getNode())) { in LowerINSERT_VECTOR_ELT()
18372 return DAG.getNode(Opc, dl, VT, N0, N1, N2); in LowerINSERT_VECTOR_ELT()
18396 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, in LowerINSERT_VECTOR_ELT()
18401 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, in LowerINSERT_VECTOR_ELT()
19614 SDValue N0 = Op.getOperand(IsStrict ? 1 : 0); in lowerUINT_TO_FP_v2i32() local
19615 assert(N0.getSimpleValueType() == MVT::v2i32 && "Unexpected input type"); in lowerUINT_TO_FP_v2i32()
19623 N0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, in lowerUINT_TO_FP_v2i32()
19626 {Op.getOperand(0), N0}); in lowerUINT_TO_FP_v2i32()
19634 N0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, in lowerUINT_TO_FP_v2i32()
19638 {Op.getOperand(0), N0}); in lowerUINT_TO_FP_v2i32()
19639 return DAG.getNode(X86ISD::CVTUI2P, DL, MVT::v2f64, N0); in lowerUINT_TO_FP_v2i32()
19646 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i64, N0); in lowerUINT_TO_FP_v2i32()
19820 SDValue N0 = Op.getOperand(OpNo); in lowerUINT_TO_FP_vec() local
19821 MVT SrcVT = N0.getSimpleValueType(); in lowerUINT_TO_FP_vec()
21810 SDValue N0 = Op.getOperand(0); in LowerFROUND() local
21822 DAG.getConstantFP(Point5Pred, dl, VT), N0); in LowerFROUND()
21823 N0 = DAG.getNode(ISD::FADD, dl, VT, N0, Adder); in LowerFROUND()
21826 return DAG.getNode(ISD::FTRUNC, dl, VT, N0); in LowerFROUND()
21962 SDValue N0 = Op.getOperand(0); in LowerFGETSIGN() local
21966 MVT OpVT = N0.getSimpleValueType(); in LowerFGETSIGN()
21972 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0); in LowerFGETSIGN()
28097 SDValue N0 = Op.getOperand(0); in LowerCTTZ() local
28105 Op = DAG.getNode(X86ISD::BSF, dl, VTs, N0); in LowerCTTZ()
28108 if (DAG.isKnownNeverZero(N0)) in LowerCTTZ()
28213 SDValue N0 = Op.getOperand(0); in LowerABS() local
28215 DAG.getConstant(0, DL, VT), N0); in LowerABS()
28216 SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_NS, DL, MVT::i8), in LowerABS()
32703 SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0); in ReplaceNodeResults() local
32705 SDValue Res = DAG.getNode(N->getOpcode(), dl, ResVT, N0, N1); in ReplaceNodeResults()
40332 SDValue N0 = V.getOperand(0); in combineCommutableSHUFP() local
40336 if (!X86::mayFoldLoad(peekThroughOneUseBitcasts(N0), Subtarget) || in combineCommutableSHUFP()
40340 return DAG.getNode(X86ISD::SHUFP, DL, VT, N1, N0, in combineCommutableSHUFP()
40353 SDValue N0 = N.getOperand(0); in combineCommutableSHUFP() local
40356 if (N0 == N1) { in combineCommutableSHUFP()
40357 if (SDValue NewSHUFP = commuteSHUFP(N, N0)) in combineCommutableSHUFP()
40360 } else if (SDValue NewSHUFP = commuteSHUFP(N, N0)) { in combineCommutableSHUFP()
40364 return DAG.getNode(X86ISD::SHUFP, DL, VT, N0, NewSHUFP, in combineCommutableSHUFP()
40377 combineBlendOfPermutes(MVT VT, SDValue N0, SDValue N1, ArrayRef<int> BlendMask, in combineBlendOfPermutes() argument
40381 if (!N0.hasOneUse() || !N1.hasOneUse()) in combineBlendOfPermutes()
40385 SDValue BC0 = peekThroughOneUseBitcasts(N0); in combineBlendOfPermutes()
40531 SDValue N0 = peekThroughOneUseBitcasts(N.getOperand(0)); in canonicalizeShuffleWithOp() local
40532 unsigned SrcOpcode = N0.getOpcode(); in canonicalizeShuffleWithOp()
40533 if (TLI.isBinOp(SrcOpcode) && IsSafeToMoveShuffle(N0, SrcOpcode)) { in canonicalizeShuffleWithOp()
40534 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0)); in canonicalizeShuffleWithOp()
40535 SDValue Op01 = peekThroughOneUseBitcasts(N0.getOperand(1)); in canonicalizeShuffleWithOp()
40550 EVT OpVT = N0.getValueType(); in canonicalizeShuffleWithOp()
40577 SDValue N0 = peekThroughOneUseBitcasts(N.getOperand(0)); in canonicalizeShuffleWithOp() local
40579 unsigned SrcOpcode = N0.getOpcode(); in canonicalizeShuffleWithOp()
40581 N0.getValueType() == N1.getValueType() && in canonicalizeShuffleWithOp()
40582 IsSafeToMoveShuffle(N0, SrcOpcode) && in canonicalizeShuffleWithOp()
40584 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0)); in canonicalizeShuffleWithOp()
40586 SDValue Op01 = peekThroughOneUseBitcasts(N0.getOperand(1)); in canonicalizeShuffleWithOp()
40606 EVT OpVT = N0.getValueType(); in canonicalizeShuffleWithOp()
40614 N0.getValueType() == N1.getValueType() && in canonicalizeShuffleWithOp()
40615 IsSafeToMoveShuffle(N0, SrcOpcode) && in canonicalizeShuffleWithOp()
40617 SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0)); in canonicalizeShuffleWithOp()
40627 EVT OpVT = N0.getValueType(); in canonicalizeShuffleWithOp()
40939 SDValue N0 = N.getOperand(0); in combineTargetShuffle() local
40943 if (N0.hasOneUse() && ISD::isNormalLoad(N0.getNode())) { in combineTargetShuffle()
40944 auto *LN = cast<LoadSDNode>(N0); in combineTargetShuffle()
40957 if (N0.hasOneUse() && N0.getOpcode() == X86ISD::VBROADCAST_LOAD) { in combineTargetShuffle()
40958 auto *LN = cast<MemSDNode>(N0); in combineTargetShuffle()
40975 if (N0.hasOneUse() && N0.getOpcode() == ISD::SCALAR_TO_VECTOR && in combineTargetShuffle()
40976 N0.getOperand(0).hasOneUse() && in combineTargetShuffle()
40977 N0.getOperand(0).getValueType() == MVT::i64) { in combineTargetShuffle()
40978 SDValue In = N0.getOperand(0); in combineTargetShuffle()
40992 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) { in combineTargetShuffle()
40993 if (auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { in combineTargetShuffle()
40995 EVT ScalarVT = N0.getOperand(0).getValueType(); in combineTargetShuffle()
41017 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) { in combineTargetShuffle()
41018 SDValue V = peekThroughOneUseBitcasts(N0); in combineTargetShuffle()
41037 SDValue N0 = N.getOperand(0); in combineTargetShuffle() local
41041 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) { in combineTargetShuffle()
41044 if (N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { in combineTargetShuffle()
41045 MVT SrcVT = N0.getOperand(0).getSimpleValueType(); in combineTargetShuffle()
41053 VT, DAG.getNode(X86ISD::BLENDI, DL, SrcVT, N0.getOperand(0), in combineTargetShuffle()
41063 if (N0.hasOneUse() && N1.hasOneUse()) { in combineTargetShuffle()
41066 SDValue LHS = peekThroughOneUseBitcasts(N0); in combineTargetShuffle()
41133 SDValue N0 = N.getOperand(0); in combineTargetShuffle() local
41136 if (N0.getOpcode() == ISD::BITCAST && in combineTargetShuffle()
41137 N0.getOperand(0).getScalarValueSizeInBits() == EltSizeInBits) { in combineTargetShuffle()
41138 SDValue Src = N0.getOperand(0); in combineTargetShuffle()
41223 SDValue N0 = N.getOperand(0); in combineTargetShuffle() local
41225 if (N0->hasOneUse()) { in combineTargetShuffle()
41226 SDValue V = peekThroughOneUseBitcasts(N0); in combineTargetShuffle()
41256 SDValue N0 = N.getOperand(0); in combineTargetShuffle() local
41267 if (N10 == N0 || in combineTargetShuffle()
41268 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
41269 if (N10 != N0) in combineTargetShuffle()
41277 return DAG.getNode(Opcode, DL, VT, N0, SclVec); in combineTargetShuffle()
41695 SDValue N0 = N->getOperand(0); in combineShuffleOfConcatUndef() local
41699 if (N0.getOpcode() != ISD::CONCAT_VECTORS || in combineShuffleOfConcatUndef()
41700 N1.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 || in combineShuffleOfConcatUndef()
41701 N1.getNumOperands() != 2 || !N0.getOperand(1).isUndef() || in combineShuffleOfConcatUndef()
41714 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, N0.getOperand(0), in combineShuffleOfConcatUndef()
42200 SDValue N0 = Op.getOperand(0); in SimplifyDemandedVectorEltsForTargetNode() local
42207 if (SimplifyDemandedVectorElts(N0, DemandedLHS, LHSUndef, LHSZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
42220 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS, in SimplifyDemandedVectorEltsForTargetNode()
42225 NewN0 = NewN0 ? NewN0 : N0; in SimplifyDemandedVectorEltsForTargetNode()
42237 SDValue N0 = Op.getOperand(0); in SimplifyDemandedVectorEltsForTargetNode() local
42244 if (SimplifyDemandedVectorElts(N0, DemandedLHS, LHSUndef, LHSZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
42256 if (N0 != N1 && !DemandedElts.isAllOnes()) { in SimplifyDemandedVectorEltsForTargetNode()
42257 SDValue NewN0 = SimplifyMultipleUseDemandedVectorElts(N0, DemandedLHS, in SimplifyDemandedVectorEltsForTargetNode()
42262 NewN0 = NewN0 ? NewN0 : N0; in SimplifyDemandedVectorEltsForTargetNode()
43804 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, in combineBitcastToBoolVector() local
43806 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, N0, in combineBitcastToBoolVector()
43817 if (SDValue N0 = combineBitcastToBoolVector(NewSrcVT, Src, DL, DAG, in combineBitcastToBoolVector() local
43822 N0, DAG.getIntPtrConstant(0, DL)); in combineBitcastToBoolVector()
43829 if (SDValue N0 = combineBitcastToBoolVector(VT, V.getOperand(0), DL, DAG, in combineBitcastToBoolVector() local
43833 return DAG.getNode(Opc, DL, VT, N0, N1); in combineBitcastToBoolVector()
43844 if (SDValue N0 = combineBitcastToBoolVector(VT, Src0, DL, DAG, Subtarget, in combineBitcastToBoolVector() local
43847 X86ISD::KSHIFTL, DL, VT, N0, in combineBitcastToBoolVector()
43864 SDValue N0 = N->getOperand(0); in combineBitcast() local
43866 EVT SrcVT = N0.getValueType(); in combineBitcast()
43877 if (SDValue V = combineBitcastvxi1(DAG, VT, N0, dl, Subtarget)) in combineBitcast()
43884 N0 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, N0); in combineBitcast()
43885 N0 = DAG.getBitcast(MVT::v8i1, N0); in combineBitcast()
43886 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, N0, in combineBitcast()
43901 if (N0.getOpcode() == ISD::CONCAT_VECTORS) { in combineBitcast()
43902 SDValue LastOp = N0.getOperand(N0.getNumOperands() - 1); in combineBitcast()
43906 SmallVector<SDValue, 4> Ops(N0->op_begin(), N0->op_end()); in combineBitcast()
43908 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops); in combineBitcast()
43909 N0 = DAG.getBitcast(MVT::i8, N0); in combineBitcast()
43910 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in combineBitcast()
43916 Ops[0] = N0; in combineBitcast()
43917 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops); in combineBitcast()
43918 N0 = DAG.getBitcast(MVT::i8, N0); in combineBitcast()
43919 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in combineBitcast()
43927 combineBitcastToBoolVector(VT, N0, SDLoc(N), DAG, Subtarget)) in combineBitcast()
43938 !Subtarget.hasDQI() && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineBitcast()
43939 N0.getOperand(0).getValueType() == MVT::v16i1 && in combineBitcast()
43940 isNullConstant(N0.getOperand(1))) in combineBitcast()
43942 DAG.getBitcast(MVT::i16, N0.getOperand(0))); in combineBitcast()
43947 if (N0.getOpcode() == X86ISD::VBROADCAST_LOAD && N0.hasOneUse() && in combineBitcast()
43949 auto *BCast = cast<MemIntrinsicSDNode>(N0); in combineBitcast()
43977 if (getTargetConstantBitsFromNode(N0, 64, UndefElts, EltBits, in combineBitcast()
43980 SDLoc DL(N0); in combineBitcast()
43992 if (N0.getOpcode() == ISD::BUILD_VECTOR && in combineBitcast()
43994 N0.getOperand(0).getValueType() == SrcVT.getScalarType()) { in combineBitcast()
43997 SDValue Op = N0.getOperand(i); in combineBitcast()
44002 SDValue N00 = N0.getOperand(0); in combineBitcast()
44013 if (N0.getOpcode() == ISD::BUILD_VECTOR && in combineBitcast()
44016 return createMMXBuildVector(cast<BuildVectorSDNode>(N0), DAG, Subtarget); in combineBitcast()
44019 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in combineBitcast()
44020 N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) && in combineBitcast()
44021 isNullConstant(N0.getOperand(1))) { in combineBitcast()
44022 SDValue N00 = N0.getOperand(0); in combineBitcast()
44029 if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) { in combineBitcast()
44030 SDLoc DL(N0); in combineBitcast()
44031 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0, in combineBitcast()
44042 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { in combineBitcast()
44043 return combinevXi1ConstantToInteger(N0, DAG); in combineBitcast()
44048 if (auto *C = dyn_cast<ConstantSDNode>(N0)) { in combineBitcast()
44050 return DAG.getConstant(1, SDLoc(N0), VT); in combineBitcast()
44052 return DAG.getConstant(0, SDLoc(N0), VT); in combineBitcast()
44063 SDValue Src = N0; in combineBitcast()
44066 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse()) in combineBitcast()
44067 Src = N0.getOperand(0); in combineBitcast()
44108 switch (N0.getOpcode()) { in combineBitcast()
44125 SDValue LogicOp0 = N0.getOperand(0); in combineBitcast()
44126 SDValue LogicOp1 = N0.getOperand(1); in combineBitcast()
44127 SDLoc DL0(N0); in combineBitcast()
44130 if (N0.hasOneUse() && LogicOp0.getOpcode() == ISD::BITCAST && in combineBitcast()
44135 unsigned Opcode = VT.isFloatingPoint() ? FPOpcode : N0.getOpcode(); in combineBitcast()
44139 if (N0.hasOneUse() && LogicOp1.getOpcode() == ISD::BITCAST && in combineBitcast()
44144 unsigned Opcode = VT.isFloatingPoint() ? FPOpcode : N0.getOpcode(); in combineBitcast()
45359 unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N0, SelectionDAG &DAG, in combineToExtendBoolVectorInReg() argument
45370 EVT InSVT = N0.getValueType().getScalarType(); in combineToExtendBoolVectorInReg()
45379 if (InSVT != MVT::i1 || N0.getOpcode() != ISD::BITCAST) in combineToExtendBoolVectorInReg()
45382 SDValue N00 = N0.getOperand(0); in combineToExtendBoolVectorInReg()
47572 SDValue N0 = N->getOperand(0); in reduceVMULWidth() local
47582 SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0); in reduceVMULWidth()
47736 SDValue N0 = N->getOperand(0); in combineMulToPMADDWD() local
47742 (((N0.getOpcode() == ISD::ZERO_EXTEND && in combineMulToPMADDWD()
47743 N0.getOperand(0).getScalarValueSizeInBits() <= 8) && in combineMulToPMADDWD()
47746 ((N0.getOpcode() == ISD::SIGN_EXTEND && in combineMulToPMADDWD()
47747 N0.getOperand(0).getScalarValueSizeInBits() <= 8) && in combineMulToPMADDWD()
47755 (N0.getOpcode() == ISD::SIGN_EXTEND && in combineMulToPMADDWD()
47756 N0.getOperand(0).getValueSizeInBits() > 128) && in combineMulToPMADDWD()
47763 DAG.ComputeMaxSignificantBits(N0) > 16) in combineMulToPMADDWD()
47803 SDValue ZeroN0 = GetZeroableOp(N0); in combineMulToPMADDWD()
47807 N0 = ZeroN0 ? ZeroN0 : N0; in combineMulToPMADDWD()
47819 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMADDWDBuilder); in combineMulToPMADDWD()
47835 SDValue N0 = N->getOperand(0); in combineMulToPMULDQ() local
47840 if (Subtarget.hasSSE41() && DAG.ComputeNumSignBits(N0) > 32 && in combineMulToPMULDQ()
47846 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULDQBuilder, in combineMulToPMULDQ()
47852 if (DAG.MaskedValueIsZero(N0, Mask) && DAG.MaskedValueIsZero(N1, Mask)) { in combineMulToPMULDQ()
47857 return SplitOpsAndApply(DAG, Subtarget, DL, VT, {N0, N1}, PMULUDQBuilder, in combineMulToPMULDQ()
48104 SDValue N0 = N->getOperand(0); in combineShiftLeft() local
48107 EVT VT = N0.getValueType(); in combineShiftLeft()
48113 if (N0.getOpcode() == ISD::VSELECT && in combineShiftLeft()
48115 SDValue Cond = N0.getOperand(0); in combineShiftLeft()
48116 SDValue N00 = N0.getOperand(1); in combineShiftLeft()
48117 SDValue N01 = N0.getOperand(2); in combineShiftLeft()
48135 N1C && N0.getOpcode() == ISD::AND && in combineShiftLeft()
48136 N0.getOperand(1).getOpcode() == ISD::Constant) { in combineShiftLeft()
48137 SDValue N00 = N0.getOperand(0); in combineShiftLeft()
48138 APInt Mask = N0.getConstantOperandAPInt(1); in combineShiftLeft()
48172 SDValue N0 = N->getOperand(0); in combineShiftRightArithmetic() local
48174 EVT VT = N0.getValueType(); in combineShiftRightArithmetic()
48186 return DAG.getNode(X86ISD::VSRAV, DL, VT, N0, ShrAmtVal); in combineShiftRightArithmetic()
48204 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() || in combineShiftRightArithmetic()
48205 N0.getOperand(1).getOpcode() != ISD::Constant) in combineShiftRightArithmetic()
48208 SDValue N00 = N0.getOperand(0); in combineShiftRightArithmetic()
48209 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic()
48241 SDValue N0 = N->getOperand(0); in combineShiftRightLogical() local
48243 EVT VT = N0.getValueType(); in combineShiftRightLogical()
48252 if (N0.getOpcode() == ISD::VSELECT && in combineShiftRightLogical()
48254 SDValue Cond = N0.getOperand(0); in combineShiftRightLogical()
48255 SDValue N00 = N0.getOperand(1); in combineShiftRightLogical()
48256 SDValue N01 = N0.getOperand(2); in combineShiftRightLogical()
48280 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) in combineShiftRightLogical()
48284 auto *AndC = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in combineShiftRightLogical()
48307 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical()
48320 SDValue N0 = N->getOperand(0); in combineHorizOpWithShuffle() local
48322 EVT SrcVT = N0.getValueType(); in combineHorizOpWithShuffle()
48325 N->isOnlyUserOf(N0.getNode()) ? peekThroughOneUseBitcasts(N0) : N0; in combineHorizOpWithShuffle()
48465 SDValue N0 = N->getOperand(0); in combineVectorPack() local
48470 assert(N0.getScalarValueSizeInBits() == SrcBitsPerElt && in combineVectorPack()
48479 if ((N0.isUndef() || N->isOnlyUserOf(N0.getNode())) && in combineVectorPack()
48481 getTargetConstantBitsFromNode(N0, SrcBitsPerElt, UndefElts0, EltBits0, in combineVectorPack()
48537 (N0.isUndef() || DAG.ComputeNumSignBits(N0) == SrcBitsPerElt) && in combineVectorPack()
48539 SDValue Not0 = N0.isUndef() ? N0 : IsNOT(N0, DAG); in combineVectorPack()
48543 MVT SrcVT = N0.getSimpleValueType(); in combineVectorPack()
48554 N0.getOpcode() == ISD::TRUNCATE && N1.isUndef() && VT == MVT::v16i8 && in combineVectorPack()
48555 N0.getOperand(0).getValueType() == MVT::v8i32) { in combineVectorPack()
48556 if ((IsSigned && DAG.ComputeNumSignBits(N0) > 8) || in combineVectorPack()
48558 DAG.MaskedValueIsZero(N0, APInt::getHighBitsSet(16, 8)))) { in combineVectorPack()
48560 return DAG.getNode(X86ISD::VTRUNC, SDLoc(N), VT, N0.getOperand(0)); in combineVectorPack()
48565 N0.getOperand(0), DAG.getUNDEF(MVT::v8i32)); in combineVectorPack()
48574 if (N0.getOpcode() == ExtOpc && in combineVectorPack()
48575 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
48576 N0.getOperand(0).getScalarValueSizeInBits() == DstBitsPerElt) { in combineVectorPack()
48577 Src0 = N0.getOperand(0); in combineVectorPack()
48584 if ((Src0 || N0.isUndef()) && (Src1 || N1.isUndef())) { in combineVectorPack()
48594 if (N0.getOpcode() == VecInRegOpc && N1.isUndef() && in combineVectorPack()
48595 N0.getOperand(0).getScalarValueSizeInBits() < DstBitsPerElt) in combineVectorPack()
48596 return getEXTEND_VECTOR_INREG(ExtOpc, SDLoc(N), VT, N0.getOperand(0), in combineVectorPack()
48663 SDValue N0 = N->getOperand(0); in combineVectorShiftVar() local
48667 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineVectorShiftVar()
48677 return getTargetVShiftByConstNode(X86Opc, SDLoc(N), VT.getSimpleVT(), N0, in combineVectorShiftVar()
48698 SDValue N0 = N->getOperand(0); in combineVectorShiftImm() local
48701 assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 && in combineVectorShiftImm()
48706 if (N0.isUndef()) in combineVectorShiftImm()
48720 return N0; in combineVectorShiftImm()
48723 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineVectorShiftImm()
48729 if (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode())) in combineVectorShiftImm()
48743 return DAG.getNode(Opcode, SDLoc(N), VT, N0.getOperand(0), in combineVectorShiftImm()
48748 if (Opcode == N0.getOpcode()) in combineVectorShiftImm()
48749 return MergeShifts(N0.getOperand(0), ShiftVal, N0.getConstantOperandVal(1)); in combineVectorShiftImm()
48752 if (Opcode == X86ISD::VSHLI && N0.getOpcode() == ISD::ADD && in combineVectorShiftImm()
48753 N0.getOperand(0) == N0.getOperand(1)) in combineVectorShiftImm()
48754 return MergeShifts(N0.getOperand(0), ShiftVal, 1); in combineVectorShiftImm()
48768 N0.getOpcode() == X86ISD::PSHUFD && in combineVectorShiftImm()
48769 N0.getConstantOperandVal(1) == getV4X86ShuffleImm({1, 1, 3, 3}) && in combineVectorShiftImm()
48770 N0->hasOneUse()) { in combineVectorShiftImm()
48771 SDValue BC = peekThroughOneUseBitcasts(N0.getOperand(0)); in combineVectorShiftImm()
48815 if (N->isOnlyUserOf(N0.getNode())) { in combineVectorShiftImm()
48816 if (SDValue C = TryConstantFold(N0)) in combineVectorShiftImm()
48821 SDValue BC = peekThroughOneUseBitcasts(N0); in combineVectorShiftImm()
48889 SDValue N0 = N->getOperand(0); in combineCompareEqual() local
48891 SDValue CMP0 = N0.getOperand(1); in combineCompareEqual()
48927 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); in combineCompareEqual()
48996 SDValue N0 = N->getOperand(0); in combineAndNotIntoANDNP() local
48999 if (SDValue Not = IsNOT(N0, DAG)) { in combineAndNotIntoANDNP()
49004 Y = N0; in combineAndNotIntoANDNP()
49059 SDValue N0 = N->getOperand(0); in combineAndShuffleNot() local
49063 if (SDValue Not = GetNot(N0)) { in combineAndShuffleNot()
49068 Y = N0; in combineAndShuffleNot()
49114 SDValue N0 = N.getOperand(0); in PromoteMaskArithmetic() local
49121 if (SDValue NN0 = PromoteMaskArithmetic(N0, DL, VT, DAG, Depth + 1)) in PromoteMaskArithmetic()
49122 N0 = NN0; in PromoteMaskArithmetic()
49125 if (N0.getOpcode() != ISD::TRUNCATE) in PromoteMaskArithmetic()
49129 if (N0.getOperand(0).getValueType() != VT) in PromoteMaskArithmetic()
49132 N0 = N0.getOperand(0); in PromoteMaskArithmetic()
49150 return DAG.getNode(N.getOpcode(), DL, VT, N0, N1); in PromoteMaskArithmetic()
49207 SDValue N0 = N->getOperand(0); in convertIntLogicToFPLogic() local
49211 if (!((N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) || in convertIntLogicToFPLogic()
49212 (N0.getOpcode() == ISD::SETCC && N1.getOpcode() == ISD::SETCC))) in convertIntLogicToFPLogic()
49215 SDValue N00 = N0.getOperand(0); in convertIntLogicToFPLogic()
49226 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) { in convertIntLogicToFPLogic()
49232 if (VT != MVT::i1 || N0.getOpcode() != ISD::SETCC || !N0.hasOneUse() || in convertIntLogicToFPLogic()
49236 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0.getOperand(2))->get(); in convertIntLogicToFPLogic()
49253 SDValue N01 = N0.getOperand(1); in convertIntLogicToFPLogic()
49272 SDValue N0 = N->getOperand(0); in combineBitOpWithMOVMSK() local
49276 if (N0.getOpcode() != X86ISD::MOVMSK || !N0.hasOneUse() || in combineBitOpWithMOVMSK()
49280 SDValue Vec0 = N0.getOperand(0); in combineBitOpWithMOVMSK()
49307 SDValue N0 = N->getOperand(0); in combineBitOpWithShift() local
49312 if (!N0.hasOneUse() || !N1.hasOneUse()) in combineBitOpWithShift()
49316 SDValue BC0 = peekThroughOneUseBitcasts(N0); in combineBitOpWithShift()
49350 SDValue N0 = N->getOperand(0); in combineBitOpWithPACK() local
49355 if (!N0.hasOneUse() || !N1.hasOneUse()) in combineBitOpWithPACK()
49359 N0 = peekThroughOneUseBitcasts(N0); in combineBitOpWithPACK()
49362 if (N0.getOpcode() != X86ISD::PACKSS || N1.getOpcode() != X86ISD::PACKSS) in combineBitOpWithPACK()
49365 MVT DstVT = N0.getSimpleValueType(); in combineBitOpWithPACK()
49369 MVT SrcVT = N0.getOperand(0).getSimpleValueType(); in combineBitOpWithPACK()
49373 if (DAG.ComputeNumSignBits(N0.getOperand(0)) != NumSrcBits || in combineBitOpWithPACK()
49374 DAG.ComputeNumSignBits(N0.getOperand(1)) != NumSrcBits || in combineBitOpWithPACK()
49380 SDValue LHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(0), N1.getOperand(0)); in combineBitOpWithPACK()
49381 SDValue RHS = DAG.getNode(Opc, DL, SrcVT, N0.getOperand(1), N1.getOperand(1)); in combineBitOpWithPACK()
49854 SDValue N0 = N->getOperand(0); in combineAnd() local
49864 DAG.getBitcast(MVT::v4f32, N0), in combineAnd()
49872 DAG.MaskedValueIsZero(N0, HiMask)) { in combineAnd()
49873 SDValue LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, N0); in combineAnd()
49909 if (N0.getOpcode() == ISD::MUL && N0.hasOneUse()) { in combineAnd()
49915 isConstOrConstSplat(N0.getOperand(1), /*AllowUndefs*/ true, in combineAnd()
49923 SDValue Neg = DAG.getNegative(N0.getOperand(0), dl, VT); in combineAnd()
49974 unsigned Opc0 = N0.getOpcode(); in combineAnd()
49976 getTargetConstantFromNode(N0.getOperand(1)) && in combineAnd()
49978 N0->hasOneUse() && N0.getOperand(1)->hasOneUse()) { in combineAnd()
49979 SDValue MaskMul = DAG.getNode(ISD::AND, dl, VT, N0.getOperand(1), N1); in combineAnd()
49980 return DAG.getNode(Opc0, dl, VT, N0.getOperand(0), MaskMul); in combineAnd()
49986 if (isOneConstant(N1) && N0->hasOneUse()) { in combineAnd()
49987 SDValue Src = N0; in combineAnd()
50053 std::tie(Bits1, Elts1) = GetDemandedMasks(N0); in combineAnd()
50055 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) || in combineAnd()
50057 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAnd()
50064 SDValue NewN0 = TLI.SimplifyMultipleUseDemandedBits(N0, Bits0, Elts0, DAG); in combineAnd()
50067 return DAG.getNode(ISD::AND, dl, VT, NewN0 ? NewN0 : N0, in combineAnd()
50073 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineAnd()
50074 isa<ConstantSDNode>(N0.getOperand(1)) && N0->hasOneUse()) { in combineAnd()
50076 SDValue SrcVec = N0.getOperand(0); in combineAnd()
50082 if (VT == SrcVecVT.getScalarType() && N0->isOnlyUserOf(SrcVec.getNode()) && in combineAnd()
50089 unsigned Idx = N0.getConstantOperandVal(1); in combineAnd()
50106 N0.getOperand(1)); in combineAnd()
50126 SDValue N0 = peekThroughBitcasts(N->getOperand(0)); in canonicalizeBitSelect() local
50128 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND) in canonicalizeBitSelect()
50134 !N0.getOperand(1).hasOneUse() || !N1.getOperand(1).hasOneUse())) in canonicalizeBitSelect()
50140 if (!getTargetConstantBitsFromNode(N0.getOperand(1), 8, UndefElts0, EltBits0, in canonicalizeBitSelect()
50165 SDValue A = DAG.getBitcast(OpVT, N0.getOperand(1)); in canonicalizeBitSelect()
50166 SDValue B = DAG.getBitcast(OpVT, N0.getOperand(0)); in canonicalizeBitSelect()
50176 DAG.getNode(X86ISD::ANDNP, DL, VT, DAG.getBitcast(VT, N0.getOperand(1)), in canonicalizeBitSelect()
50186 SDValue N0 = N->getOperand(0); in matchLogicBlend() local
50191 std::swap(N0, N1); in matchLogicBlend()
50194 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP) in matchLogicBlend()
50201 if (N0.getOperand(0) == Mask) in matchLogicBlend()
50202 Y = N0.getOperand(1); in matchLogicBlend()
50203 else if (N0.getOperand(1) == Mask) in matchLogicBlend()
50204 Y = N0.getOperand(0); in matchLogicBlend()
50402 SDValue N0 = Node->getOperand(0); in foldMaskedMerge() local
50403 if (N0->getOpcode() != ISD::AND || !N0->hasOneUse()) in foldMaskedMerge()
50410 SDValue N00 = N0->getOperand(0); in foldMaskedMerge()
50411 SDValue N01 = N0->getOperand(1); in foldMaskedMerge()
50633 static SDValue combineOrXorWithSETCC(SDNode *N, SDValue N0, SDValue N1, in combineOrXorWithSETCC() argument
50644 if (N0.getOpcode() == ISD::ZERO_EXTEND && in combineOrXorWithSETCC()
50645 N0.getOperand(0).getOpcode() == X86ISD::SETCC && N0.hasOneUse()) { in combineOrXorWithSETCC()
50652 if (SDValue R = combineAddOrSubToADCOrSBB(IsSub, DL, VT, N1, N0, DAG)) in combineOrXorWithSETCC()
50659 if (N->getOpcode() == ISD::XOR && N0.getOpcode() == X86ISD::PCMPEQ && in combineOrXorWithSETCC()
50660 N0.getOperand(0).getOpcode() == ISD::AND && in combineOrXorWithSETCC()
50661 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()) && in combineOrXorWithSETCC()
50666 if (getTargetConstantBitsFromNode(N0.getOperand(0).getOperand(1), in combineOrXorWithSETCC()
50674 return DAG.getNode(X86ISD::PCMPEQ, SDLoc(N), VT, N0.getOperand(0), in combineOrXorWithSETCC()
50675 N0.getOperand(0).getOperand(1)); in combineOrXorWithSETCC()
50685 SDValue N0 = N->getOperand(0); in combineOr() local
50695 DAG.getBitcast(MVT::v4f32, N0), in combineOr()
50751 N0.getOpcode() == ISD::SUB && N0.hasOneUse() && in combineOr()
50752 isNullConstant(N0.getOperand(0))) { in combineOr()
50753 SDValue Cond = N0.getOperand(1); in combineOr()
50778 if (N0.getOpcode() == X86ISD::KSHIFTL || N1.getOpcode() == X86ISD::KSHIFTL) { in combineOr()
50784 DAG.MaskedVectorIsZero(N0, UpperElts)) { in combineOr()
50787 extractSubVector(N0, 0, DAG, dl, HalfElts), in combineOr()
50790 if (NumElts >= 16 && N0.getOpcode() == X86ISD::KSHIFTL && in combineOr()
50791 N0.getConstantOperandAPInt(1) == HalfElts && in combineOr()
50796 extractSubVector(N0.getOperand(0), 0, DAG, dl, HalfElts)); in combineOr()
50823 if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) { in combineOr()
50835 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG)) in combineOr()
50851 SDValue N0 = N->getOperand(0); in foldXorTruncShiftIntoCmp() local
50855 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse()) in foldXorTruncShiftIntoCmp()
50863 SDValue Shift = N0.getOperand(0); in foldXorTruncShiftIntoCmp()
51932 auto GetShuffle = [&](SDValue Op, SDValue &N0, SDValue &N1, in isHorizontalBinOp()
51951 N0 = !SrcOps.empty() ? SrcOps[0] : SDValue(); in isHorizontalBinOp()
51957 std::tie(N0, N1) = DAG.SplitVector(SrcOps[0], SDLoc(Op)); in isHorizontalBinOp()
52347 auto TruncateArithmetic = [&](SDValue N0, SDValue N1) { in combineTruncatedArithmetic() argument
52348 SDValue Trunc0 = DAG.getNode(ISD::TRUNCATE, DL, VT, N0); in combineTruncatedArithmetic()
52499 SDValue N0 = SSatVal.getOperand(0); in detectPMADDUBSW() local
52502 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL) in detectPMADDUBSW()
52505 SDValue N00 = N0.getOperand(0); in detectPMADDUBSW()
52506 SDValue N01 = N0.getOperand(1); in detectPMADDUBSW()
52997 SDValue N0 = N->getOperand(0); in combineXorSubCTLZ() local
53000 if (N0.getOpcode() != ISD::CTLZ_ZERO_UNDEF && in combineXorSubCTLZ()
53009 OpSizeTM1 = N0; in combineXorSubCTLZ()
53013 OpCTLZ = N0; in combineXorSubCTLZ()
53044 SDValue N0 = N->getOperand(0); in combineXor() local
53053 DAG.getBitcast(MVT::v4f32, N0), in combineXor()
53081 if (SDValue R = combineOrXorWithSETCC(N, N0, N1, DAG)) in combineXor()
53089 if (llvm::isAllOnesConstant(N1) && N0.getOpcode() == ISD::BITCAST && in combineXor()
53090 N0.getOperand(0).getValueType().isVector() && in combineXor()
53091 N0.getOperand(0).getValueType().getVectorElementType() == MVT::i1 && in combineXor()
53092 TLI.isTypeLegal(N0.getOperand(0).getValueType()) && N0.hasOneUse()) { in combineXor()
53094 VT, DAG.getNOT(DL, N0.getOperand(0), N0.getOperand(0).getValueType())); in combineXor()
53101 N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.getOperand(0).isUndef() && in combineXor()
53102 TLI.isTypeLegal(N0.getOperand(1).getValueType())) { in combineXor()
53104 ISD::INSERT_SUBVECTOR, DL, VT, N0.getOperand(0), in combineXor()
53105 DAG.getNOT(DL, N0.getOperand(1), N0.getOperand(1).getValueType()), in combineXor()
53106 N0.getOperand(2)); in combineXor()
53112 if ((N0.getOpcode() == ISD::TRUNCATE || N0.getOpcode() == ISD::ZERO_EXTEND) && in combineXor()
53113 N0.getOperand(0).getOpcode() == N->getOpcode()) { in combineXor()
53114 SDValue TruncExtSrc = N0.getOperand(0); in combineXor()
53134 SDValue N0 = N->getOperand(0); in combineBITREVERSE() local
53138 if (VT.isInteger() && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse()) { in combineBITREVERSE()
53139 SDValue Src = N0.getOperand(0); in combineBITREVERSE()
53163 SDValue N0 = N->getOperand(0); in combineAVG() local
53174 N0 = DAG.getNode(ISD::XOR, DL, VT, N0, SignMask); in combineAVG()
53177 DAG.getNode(ISD::AVGCEILU, DL, VT, N0, N1), SignMask); in combineAVG()
53223 SDValue N0 = N->getOperand(0); in combineFAndFNotToFAndn() local
53242 if (N0.getOpcode() == X86ISD::FXOR && isAllOnesConstantFP(N0.getOperand(1))) in combineFAndFNotToFAndn()
53243 return DAG.getNode(X86ISD::FANDN, DL, VT, N0.getOperand(0), N1); in combineFAndFNotToFAndn()
53247 return DAG.getNode(X86ISD::FANDN, DL, VT, N1.getOperand(0), N0); in combineFAndFNotToFAndn()
53464 SDValue N0 = N->getOperand(0); in combineAndnp() local
53473 if (N0.isUndef() || N1.isUndef()) in combineAndnp()
53477 if (ISD::isBuildVectorAllZeros(N0.getNode())) in combineAndnp()
53486 return DAG.getNOT(DL, N0, VT); in combineAndnp()
53489 if (SDValue Not = IsNOT(N0, DAG)) in combineAndnp()
53497 DL, DAG.getNode(ISD::OR, DL, VT, N0, DAG.getBitcast(VT, Not)), VT); in combineAndnp()
53502 if (getTargetConstantBitsFromNode(N0, EltSizeInBits, Undefs0, EltBits0, in combineAndnp()
53517 if (N0->hasOneUse()) { in combineAndnp()
53518 SDValue BC0 = peekThroughOneUseBitcasts(N0); in combineAndnp()
53563 std::tie(Bits1, Elts1) = GetDemandedMasks(N0, true); in combineAndnp()
53566 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) || in combineAndnp()
53568 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAndnp()
53641 SDValue N0 = N->getOperand(0); in combineSextInRegCmov() local
53650 if ((N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && in combineSextInRegCmov()
53651 N0.hasOneUse()) { in combineSextInRegCmov()
53652 IntermediateBitwidthOp = N0; in combineSextInRegCmov()
53653 N0 = N0.getOperand(0); in combineSextInRegCmov()
53657 if (N0.getOpcode() != X86ISD::CMOV || !N0.hasOneUse()) in combineSextInRegCmov()
53660 SDValue CMovOp0 = N0.getOperand(0); in combineSextInRegCmov()
53661 SDValue CMovOp1 = N0.getOperand(1); in combineSextInRegCmov()
53689 N0.getOperand(2), N0.getOperand(3)); in combineSextInRegCmov()
53705 SDValue N0 = N->getOperand(0); in combineSignExtendInReg() local
53715 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND || in combineSignExtendInReg()
53716 N0.getOpcode() == ISD::SIGN_EXTEND)) { in combineSignExtendInReg()
53717 SDValue N00 = N0.getOperand(0); in combineSignExtendInReg()
53727 if (SDValue Promote = PromoteMaskArithmetic(N0, dl, DAG, Subtarget)) in combineSignExtendInReg()
53868 SDValue N0 = N->getOperand(0); in combineExtSetcc() local
53873 if (!Subtarget.hasAVX512() || !VT.isVector() || N0.getOpcode() != ISD::SETCC) in combineExtSetcc()
53883 if (N0.getOperand(0).getValueType().getVectorElementType() == MVT::f16) in combineExtSetcc()
53892 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); in combineExtSetcc()
53897 EVT N00VT = N0.getOperand(0).getValueType(); in combineExtSetcc()
53902 SDValue Res = DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); in combineExtSetcc()
53905 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType()); in combineExtSetcc()
53913 SDValue N0 = N->getOperand(0); in combineSext() local
53919 N0.getOpcode() == X86ISD::SETCC_CARRY) { in combineSext()
53920 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0), in combineSext()
53921 N0->getOperand(1)); in combineSext()
53922 bool ReplaceOtherUses = !N0.hasOneUse(); in combineSext()
53926 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), in combineSext()
53927 N0.getValueType(), Setcc); in combineSext()
53928 DCI.CombineTo(N0.getNode(), Trunc); in combineSext()
53943 if (SDValue V = combineToExtendBoolVectorInReg(N->getOpcode(), DL, VT, N0, in combineSext()
53951 if (N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in combineSext()
53952 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0)); in combineSext()
54129 SDValue N0 = N->getOperand(0); in combineZext() local
54135 N0.getOpcode() == X86ISD::SETCC_CARRY) { in combineZext()
54136 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0), in combineZext()
54137 N0->getOperand(1)); in combineZext()
54138 bool ReplaceOtherUses = !N0.hasOneUse(); in combineZext()
54142 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), in combineZext()
54143 N0.getValueType(), Setcc); in combineZext()
54144 DCI.CombineTo(N0.getNode(), Trunc); in combineZext()
54157 if (SDValue V = combineToExtendBoolVectorInReg(N->getOpcode(), dl, VT, N0, in combineZext()
54172 if (N0.getOpcode() == X86ISD::PACKUS && N0.getValueSizeInBits() == 128 && in combineZext()
54173 VT.getScalarSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits()) { in combineZext()
54174 SDValue N00 = N0.getOperand(0); in combineZext()
54175 SDValue N01 = N0.getOperand(1); in combineZext()
54229 auto MatchOrCmpEq = [&](SDValue N0, SDValue N1) { in combineSetCC() argument
54230 if (N0.getOpcode() == ISD::OR && N0->hasOneUse()) { in combineSetCC()
54231 if (N0.getOperand(0) == N1) in combineSetCC()
54233 N0.getOperand(1)); in combineSetCC()
54234 if (N0.getOperand(1) == N1) in combineSetCC()
54236 N0.getOperand(0)); in combineSetCC()
54247 auto MatchAndCmpEq = [&](SDValue N0, SDValue N1) { in combineSetCC() argument
54248 if (N0.getOpcode() == ISD::AND && N0->hasOneUse()) { in combineSetCC()
54249 if (N0.getOperand(0) == N1) in combineSetCC()
54251 DAG.getNOT(DL, N0.getOperand(1), OpVT)); in combineSetCC()
54252 if (N0.getOperand(1) == N1) in combineSetCC()
54254 DAG.getNOT(DL, N0.getOperand(0), OpVT)); in combineSetCC()
55319 auto MatchGeneric = [&](SDValue N0, SDValue N1, bool Negate) { in combineX86AddSub() argument
55320 SDValue Ops[] = {N0, N1}; in combineX86AddSub()
55509 SDValue N0 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Mul.getOperand(0)); in matchPMADDWD() local
55520 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { N0, N1 }, PMADDBuilder); in matchPMADDWD()
55526 static SDValue matchPMADDWD_2(SelectionDAG &DAG, SDValue N0, SDValue N1, in matchPMADDWD_2() argument
55532 if (N0.getOpcode() != ISD::MUL || N1.getOpcode() != ISD::MUL) in matchPMADDWD_2()
55540 SDValue N00 = N0.getOperand(0); in matchPMADDWD_2()
55541 SDValue N01 = N0.getOperand(1); in matchPMADDWD_2()
55666 static SDValue combineAddOfPMADDWD(SelectionDAG &DAG, SDValue N0, SDValue N1, in combineAddOfPMADDWD() argument
55668 if (N0.getOpcode() != N1.getOpcode() || N0.getOpcode() != X86ISD::VPMADDWD) in combineAddOfPMADDWD()
55676 MVT OpVT = N0.getOperand(0).getSimpleValueType(); in combineAddOfPMADDWD()
55681 DAG.MaskedValueIsZero(N0.getOperand(0), DemandedBits, DemandedHiElts) || in combineAddOfPMADDWD()
55682 DAG.MaskedValueIsZero(N0.getOperand(1), DemandedBits, DemandedHiElts); in combineAddOfPMADDWD()
55700 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(0), N1.getOperand(0), Mask); in combineAddOfPMADDWD()
55702 DAG.getVectorShuffle(OpVT, DL, N0.getOperand(1), N1.getOperand(1), Mask); in combineAddOfPMADDWD()
55849 SDValue N0 = N->getOperand(0); in combineSubABS() local
55882 return DAG.getNode(ISD::ADD, DL, VT, N0, Cmov); in combineSubABS()
58088 SDValue N0 = Op.getOperand(0); in IsDesirableToPromoteOp() local
58090 if (X86::mayFoldLoad(N0, Subtarget) && IsFoldableRMW(N0, Op)) in IsDesirableToPromoteOp()
58102 SDValue N0 = Op.getOperand(0); in IsDesirableToPromoteOp() local
58106 (!Commute || !isa<ConstantSDNode>(N0) || in IsDesirableToPromoteOp()
58109 if (X86::mayFoldLoad(N0, Subtarget) && in IsDesirableToPromoteOp()
58111 (Op.getOpcode() != ISD::MUL && IsFoldableRMW(N0, Op)))) in IsDesirableToPromoteOp()
58113 if (IsFoldableAtomicRMW(N0, Op) || in IsDesirableToPromoteOp()