Lines Matching refs:N0
3523 SDValue N0 = Op.getOperand(0); in LowerFP_TO_FP16() local
3526 if (N0.getValueType() == MVT::f32) in LowerFP_TO_FP16()
3527 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
3534 assert(N0.getSimpleValueType() == MVT::f64); in LowerFP_TO_FP16()
3542 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0); in LowerFP_TO_FP16()
3910 SDValue N0 = N->getOperand(0); in performAssertSZExtCombine() local
3914 if (N0.getOpcode() == ISD::TRUNCATE) { in performAssertSZExtCombine()
3919 SDValue Src = N0.getOperand(0); in performAssertSZExtCombine()
4235 SDValue N0, SDValue N1, unsigned Size, bool Signed) { in getMul24() argument
4238 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4244 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
4245 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
4278 SDValue N0 = N->getOperand(0); in performMulCombine() local
4300 if (SDValue MulOper = IsFoldableAdd(N0)) { in performMulCombine()
4306 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); in performMulCombine()
4307 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
4318 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulCombine()
4319 N0 = N0.getOperand(0); in performMulCombine()
4326 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) { in performMulCombine()
4327 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
4329 Mul = getMul24(DAG, DL, N0, N1, Size, false); in performMulCombine()
4330 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine()
4331 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
4333 Mul = getMul24(DAG, DL, N0, N1, Size, true); in performMulCombine()
4353 SDValue N0 = N->getOperand(0); in performMulLoHiCombine() local
4360 if (N0.getOpcode() == ISD::ANY_EXTEND) in performMulLoHiCombine()
4361 N0 = N0.getOperand(0); in performMulLoHiCombine()
4370 if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulLoHiCombine()
4371 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulLoHiCombine()
4377 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) { in performMulLoHiCombine()
4378 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulLoHiCombine()
4387 SDValue Lo = DAG.getNode(LoOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
4388 SDValue Hi = DAG.getNode(HiOpcode, DL, MVT::i32, N0, N1); in performMulLoHiCombine()
4412 SDValue N0 = N->getOperand(0); in performMulhsCombine() local
4415 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
4418 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulhsCombine()
4421 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1); in performMulhsCombine()
4445 SDValue N0 = N->getOperand(0); in performMulhuCombine() local
4448 if (!isU24(N0, DAG) || !isU24(N1, DAG)) in performMulhuCombine()
4451 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulhuCombine()
4454 SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1); in performMulhuCombine()
4726 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) { in shouldFoldFNegIntoSrc() argument
4731 if (N0.hasOneUse()) { in shouldFoldFNegIntoSrc()
4737 if (fnegFoldsIntoOp(N0.getNode()) && in shouldFoldFNegIntoSrc()
4738 (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode()))) in shouldFoldFNegIntoSrc()
4748 SDValue N0 = N->getOperand(0); in performFNegCombine() local
4751 unsigned Opc = N0.getOpcode(); in performFNegCombine()
4753 if (!shouldFoldFNegIntoSrc(N, N0)) in performFNegCombine()
4759 if (!mayIgnoreSignedZero(N0)) in performFNegCombine()
4763 SDValue LHS = N0.getOperand(0); in performFNegCombine()
4764 SDValue RHS = N0.getOperand(1); in performFNegCombine()
4776 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4779 if (!N0.hasOneUse()) in performFNegCombine()
4780 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4787 SDValue LHS = N0.getOperand(0); in performFNegCombine()
4788 SDValue RHS = N0.getOperand(1); in performFNegCombine()
4797 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4800 if (!N0.hasOneUse()) in performFNegCombine()
4801 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4807 if (!mayIgnoreSignedZero(N0)) in performFNegCombine()
4811 SDValue LHS = N0.getOperand(0); in performFNegCombine()
4812 SDValue MHS = N0.getOperand(1); in performFNegCombine()
4813 SDValue RHS = N0.getOperand(2); in performFNegCombine()
4830 if (!N0.hasOneUse()) in performFNegCombine()
4831 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4847 SDValue LHS = N0.getOperand(0); in performFNegCombine()
4848 SDValue RHS = N0.getOperand(1); in performFNegCombine()
4859 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4862 if (!N0.hasOneUse()) in performFNegCombine()
4863 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4869 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
4871 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
4875 if (!N0.hasOneUse()) { in performFNegCombine()
4877 DAG.ReplaceAllUsesWith(N0, Neg); in performFNegCombine()
4896 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine()
4903 if (!N0.hasOneUse()) in performFNegCombine()
4909 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
4912 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine()
4917 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine()
4920 if (!N0.hasOneUse()) in performFNegCombine()
4925 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
4933 SDValue Src = N0.getOperand(0); in performFNegCombine()
4948 SDValue BCSrc = N0.getOperand(0); in performFNegCombine()
4976 if (!N0.hasOneUse()) in performFNegCombine()
4977 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result)); in performFNegCombine()
5010 SDValue N0 = N->getOperand(0); in performFAbsCombine() local
5012 if (!N0.hasOneUse()) in performFAbsCombine()
5015 switch (N0.getOpcode()) { in performFAbsCombine()
5019 SDValue Src = N0.getOperand(0); in performFAbsCombine()
5254 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
5261 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); in PerformDAGCombine()
6007 Register N0, Register N1) const { in isReassocProfitable() argument
6008 return MRI.hasOneNonDBGUse(N0); // FIXME: handle regbanks in isReassocProfitable()