Lines Matching refs:N0
9607 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
9609 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
9610 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9618 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
9620 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9632 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
9636 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
9641 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9648 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
9651 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
9655 std::swap(N0, N1); in LowerMUL()
9676 Op0 = SkipExtensionForVMULL(N0, DAG); in LowerMUL()
9691 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
9692 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
9694 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
9732 static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl, in LowerSDIV_v4i16() argument
9740 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9742 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
9759 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
9760 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9762 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
9763 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
9766 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9767 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
9768 return N0; in LowerSDIV_v4i16()
9778 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
9783 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
9786 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9790 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9795 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
9798 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9799 N0 = LowerCONCAT_VECTORS(N0, DAG, ST); in LowerSDIV()
9801 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
9802 return N0; in LowerSDIV()
9804 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
9815 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
9820 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
9823 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
9827 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
9832 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
9835 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
9836 N0 = LowerCONCAT_VECTORS(N0, DAG, ST); in LowerUDIV()
9838 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
9841 N0); in LowerUDIV()
9842 return N0; in LowerUDIV()
9848 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
9850 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
9872 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
9873 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
9875 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
9876 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
9879 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
9880 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
9881 return N0; in LowerUDIV()
12619 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
12621 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
12622 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
12625 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
12642 static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADD() argument
12646 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || in AddCombineToVPADD()
12647 N0 == N1) in AddCombineToVPADD()
12658 SDNode *Unzip = N0.getNode(); in AddCombineToVPADD()
12670 static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineVUZPToVPADDL() argument
12674 if (!(N0.getOpcode() == ISD::SIGN_EXTEND && in AddCombineVUZPToVPADDL()
12676 !(N0.getOpcode() == ISD::ZERO_EXTEND && in AddCombineVUZPToVPADDL()
12680 SDValue N00 = N0.getOperand(0); in AddCombineVUZPToVPADDL()
12691 !N0.getValueType().is128BitVector()) in AddCombineVUZPToVPADDL()
12703 if (N0.getOpcode() == ISD::SIGN_EXTEND) in AddCombineVUZPToVPADDL()
12723 AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineBUILD_VECTORToVPADDL() argument
12729 || N0.getOpcode() != ISD::BUILD_VECTOR in AddCombineBUILD_VECTORToVPADDL()
12745 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in AddCombineBUILD_VECTORToVPADDL()
12747 SDValue Vec = N0->getOperand(0)->getOperand(0); in AddCombineBUILD_VECTORToVPADDL()
12754 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { in AddCombineBUILD_VECTORToVPADDL()
12755 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT in AddCombineBUILD_VECTORToVPADDL()
12758 SDValue ExtVec0 = N0->getOperand(i); in AddCombineBUILD_VECTORToVPADDL()
13545 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
13549 if (SDValue Result = AddCombineToVPADD(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13553 if (SDValue Result = AddCombineVUZPToVPADDL(N, N0, N1, DCI, Subtarget)) in PerformADDCombineWithOperands()
13555 if (SDValue Result = AddCombineBUILD_VECTORToVPADDL(N, N0, N1, DCI, in PerformADDCombineWithOperands()
13560 if (N0.getNode()->hasOneUse()) in PerformADDCombineWithOperands()
13561 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI)) in PerformADDCombineWithOperands()
13568 SDValue N0 = N->getOperand(0); in TryDistrubutionADDVecReduce() local
13584 auto DistrubuteAddAddVecReduce = [&](SDValue N0, SDValue N1) { in TryDistrubutionADDVecReduce() argument
13588 if (VT == MVT::i32 && N1.getOpcode() == ISD::ADD && !IsVecReduce(N0) && in TryDistrubutionADDVecReduce()
13590 !isa<ConstantSDNode>(N0) && N1->hasOneUse()) { in TryDistrubutionADDVecReduce()
13591 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0, N1.getOperand(0)); in TryDistrubutionADDVecReduce()
13596 if (VT == MVT::i32 && N0.getOpcode() == ISD::ADD && in TryDistrubutionADDVecReduce()
13597 N1.getOpcode() == ISD::ADD && N0->hasOneUse() && N1->hasOneUse()) { in TryDistrubutionADDVecReduce()
13599 if (!IsVecReduce(N0.getOperand(N0RedOp))) { in TryDistrubutionADDVecReduce()
13601 if (!IsVecReduce(N0.getOperand(N0RedOp))) in TryDistrubutionADDVecReduce()
13611 SDValue Add0 = DAG.getNode(ISD::ADD, dl, VT, N0.getOperand(1 - N0RedOp), in TryDistrubutionADDVecReduce()
13614 DAG.getNode(ISD::ADD, dl, VT, Add0, N0.getOperand(N0RedOp)); in TryDistrubutionADDVecReduce()
13619 if (SDValue R = DistrubuteAddAddVecReduce(N0, N1)) in TryDistrubutionADDVecReduce()
13621 if (SDValue R = DistrubuteAddAddVecReduce(N1, N0)) in TryDistrubutionADDVecReduce()
13628 auto DistrubuteVecReduceLoad = [&](SDValue N0, SDValue N1, bool IsForward) { in TryDistrubutionADDVecReduce() argument
13632 auto IsKnownOrderedLoad = [&](SDValue N0, SDValue N1) { in TryDistrubutionADDVecReduce() argument
13635 if (N0.getOpcode() == ISD::MUL) in TryDistrubutionADDVecReduce()
13636 N0 = N0.getOperand(0); in TryDistrubutionADDVecReduce()
13642 LoadSDNode *Load0 = dyn_cast<LoadSDNode>(N0); in TryDistrubutionADDVecReduce()
13664 if (N0.getOpcode() == ISD::ADD && N0->hasOneUse()) { in TryDistrubutionADDVecReduce()
13665 if (IsVecReduce(N0.getOperand(0)) && IsVecReduce(N0.getOperand(1))) { in TryDistrubutionADDVecReduce()
13666 int IsBefore = IsKnownOrderedLoad(N0.getOperand(0).getOperand(0), in TryDistrubutionADDVecReduce()
13667 N0.getOperand(1).getOperand(0)); in TryDistrubutionADDVecReduce()
13669 X = N0.getOperand(0); in TryDistrubutionADDVecReduce()
13670 N0 = N0.getOperand(1); in TryDistrubutionADDVecReduce()
13672 X = N0.getOperand(1); in TryDistrubutionADDVecReduce()
13673 N0 = N0.getOperand(0); in TryDistrubutionADDVecReduce()
13676 } else if (IsVecReduce(N0.getOperand(0))) { in TryDistrubutionADDVecReduce()
13677 X = N0.getOperand(1); in TryDistrubutionADDVecReduce()
13678 N0 = N0.getOperand(0); in TryDistrubutionADDVecReduce()
13679 } else if (IsVecReduce(N0.getOperand(1))) { in TryDistrubutionADDVecReduce()
13680 X = N0.getOperand(0); in TryDistrubutionADDVecReduce()
13681 N0 = N0.getOperand(1); in TryDistrubutionADDVecReduce()
13684 } else if (IsForward && IsVecReduce(N0) && IsVecReduce(N1) && in TryDistrubutionADDVecReduce()
13685 IsKnownOrderedLoad(N0.getOperand(0), N1.getOperand(0)) < 0) { in TryDistrubutionADDVecReduce()
13690 return DAG.getNode(ISD::ADD, dl, VT, N1, N0); in TryDistrubutionADDVecReduce()
13694 if (!IsVecReduce(N0) || !IsVecReduce(N1)) in TryDistrubutionADDVecReduce()
13697 if (IsKnownOrderedLoad(N1.getOperand(0), N0.getOperand(0)) >= 0) in TryDistrubutionADDVecReduce()
13702 return DAG.getNode(ISD::ADD, dl, VT, Add0, N0); in TryDistrubutionADDVecReduce()
13704 if (SDValue R = DistrubuteVecReduceLoad(N0, N1, true)) in TryDistrubutionADDVecReduce()
13706 if (SDValue R = DistrubuteVecReduceLoad(N1, N0, false)) in TryDistrubutionADDVecReduce()
13720 SDValue N0 = N->getOperand(0); in PerformADDVecReduce() local
13764 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N0, N1)) in PerformADDVecReduce()
13766 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N0, N1)) in PerformADDVecReduce()
13768 if (SDValue M = MakeVecReduce(ARMISD::VADDLVs, ARMISD::VADDLVAs, N1, N0)) in PerformADDVecReduce()
13770 if (SDValue M = MakeVecReduce(ARMISD::VADDLVu, ARMISD::VADDLVAu, N1, N0)) in PerformADDVecReduce()
13772 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N0, N1)) in PerformADDVecReduce()
13774 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N0, N1)) in PerformADDVecReduce()
13776 if (SDValue M = MakeVecReduce(ARMISD::VADDLVps, ARMISD::VADDLVAps, N1, N0)) in PerformADDVecReduce()
13778 if (SDValue M = MakeVecReduce(ARMISD::VADDLVpu, ARMISD::VADDLVApu, N1, N0)) in PerformADDVecReduce()
13780 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N0, N1)) in PerformADDVecReduce()
13782 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N0, N1)) in PerformADDVecReduce()
13784 if (SDValue M = MakeVecReduce(ARMISD::VMLALVs, ARMISD::VMLALVAs, N1, N0)) in PerformADDVecReduce()
13786 if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0)) in PerformADDVecReduce()
13788 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) in PerformADDVecReduce()
13790 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N0, N1)) in PerformADDVecReduce()
13792 if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) in PerformADDVecReduce()
13794 if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N1, N0)) in PerformADDVecReduce()
14025 SDValue N0 = N->getOperand(0); in PerformADDCombine() local
14036 if (SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget)) in PerformADDCombine()
14040 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
14068 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
14073 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI)) in PerformSUBCombine()
14125 SDValue N0 = N->getOperand(0); in PerformVMULCombine() local
14127 unsigned Opcode = N0.getOpcode(); in PerformVMULCombine()
14134 std::swap(N0, N1); in PerformVMULCombine()
14137 if (N0 == N1) in PerformVMULCombine()
14142 SDValue N00 = N0->getOperand(0); in PerformVMULCombine()
14143 SDValue N01 = N0->getOperand(1); in PerformVMULCombine()
14155 SDValue N0 = N->getOperand(0); in PerformMVEVMULLCombine() local
14196 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine()
14203 if (SDValue Op0 = IsZeroExt(N0)) { in PerformMVEVMULLCombine()
14319 SDNode *N0 = N->getOperand(0).getNode(); in CombineANDShift() local
14320 if (!N0->hasOneUse()) in CombineANDShift()
14323 if (N0->getOpcode() != ISD::SHL && N0->getOpcode() != ISD::SRL) in CombineANDShift()
14326 bool LeftShift = N0->getOpcode() == ISD::SHL; in CombineANDShift()
14328 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1)); in CombineANDShift()
14354 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
14365 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
14378 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
14391 SDValue SHL = DAG.getNode(ISD::SRL, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
14403 SDValue And = DAG.getNode(ISD::AND, DL, MVT::i32, N0->getOperand(0), in CombineANDShift()
14530 SDValue N0 = N->getOperand(0); in PerformORCombineToBFI() local
14547 SDValue N00 = N0.getOperand(0); in PerformORCombineToBFI()
14552 SDValue MaskOp = N0.getOperand(1); in PerformORCombineToBFI()
14685 SDValue N0 = N->getOperand(0); in PerformORCombine_i1() local
14695 if (!(IsFreelyInvertable(N0) || IsFreelyInvertable(N1))) in PerformORCombine_i1()
14698 SDValue NewN0 = DAG.getLogicalNOT(DL, N0, VT); in PerformORCombine_i1()
14749 SDValue N0 = N->getOperand(0); in PerformORCombine() local
14759 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) in PerformORCombine()
14767 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); in PerformORCombine()
14783 N0->getOperand(1), in PerformORCombine()
14784 N0->getOperand(0), in PerformORCombine()
14794 if (N0.getOpcode() == ISD::AND && N0.hasOneUse()) { in PerformORCombine()
14825 SDValue N0 = N->getOperand(0); in PerformXORCombine() local
14829 (N0->getOpcode() == ARMISD::VCMP || N0->getOpcode() == ARMISD::VCMPZ)) { in PerformXORCombine()
14830 if (CanInvertMVEVCMP(N0)) { in PerformXORCombine()
14831 SDLoc DL(N0); in PerformXORCombine()
14832 ARMCC::CondCodes CC = ARMCC::getOppositeCondition(getVCMPCondCode(N0)); in PerformXORCombine()
14835 Ops.push_back(N0->getOperand(0)); in PerformXORCombine()
14836 if (N0->getOpcode() == ARMISD::VCMP) in PerformXORCombine()
14837 Ops.push_back(N0->getOperand(1)); in PerformXORCombine()
14839 return DAG.getNode(N0->getOpcode(), DL, N0->getValueType(0), Ops); in PerformXORCombine()
14911 SDValue N0 = N->getOperand(0); in PerformBFICombine() local
14965 APInt ToMask2 = ~N0.getConstantOperandAPInt(2); in PerformBFICombine()
14967 if (!N0.hasOneUse() || (ToMask1 & ToMask2) != 0 || in PerformBFICombine()
14973 SDValue BFI1 = DAG.getNode(ARMISD::BFI, dl, VT, N0.getOperand(0), in PerformBFICombine()
14975 return DAG.getNode(ARMISD::BFI, dl, VT, BFI1, N0.getOperand(1), in PerformBFICombine()
14976 N0.getOperand(2)); in PerformBFICombine()
15224 SDValue N0 = N->getOperand(0); in PerformVMOVrhCombine() local
15228 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0)) { in PerformVMOVrhCombine()
15234 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { in PerformVMOVrhCombine()
15235 LoadSDNode *LN0 = cast<LoadSDNode>(N0); in PerformVMOVrhCombine()
15241 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); in PerformVMOVrhCombine()
15246 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformVMOVrhCombine()
15247 isa<ConstantSDNode>(N0->getOperand(1))) in PerformVMOVrhCombine()
15248 return DAG.getNode(ARMISD::VGETLANEu, SDLoc(N), VT, N0->getOperand(0), in PerformVMOVrhCombine()
15249 N0->getOperand(1)); in PerformVMOVrhCombine()
17102 SDValue N0 = N->getOperand(0); in PerformVECREDUCE_ADDCombine() local
17106 if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD && in PerformVECREDUCE_ADDCombine()
17107 (N0.getValueType() == MVT::v4i32 || N0.getValueType() == MVT::v8i16 || in PerformVECREDUCE_ADDCombine()
17108 N0.getValueType() == MVT::v16i8)) { in PerformVECREDUCE_ADDCombine()
17109 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0)); in PerformVECREDUCE_ADDCombine()
17110 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1)); in PerformVECREDUCE_ADDCombine()
17145 if (ResVT != RetTy || N0->getOpcode() != ExtendCode) in PerformVECREDUCE_ADDCombine()
17147 SDValue A = N0->getOperand(0); in PerformVECREDUCE_ADDCombine()
17154 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17155 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
17157 Mask = N0->getOperand(0); in PerformVECREDUCE_ADDCombine()
17158 SDValue Ext = N0->getOperand(1); in PerformVECREDUCE_ADDCombine()
17178 SDValue Mul = N0; in PerformVECREDUCE_ADDCombine()
17206 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17207 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
17209 Mask = N0->getOperand(0); in PerformVECREDUCE_ADDCombine()
17210 SDValue Mul = N0->getOperand(1); in PerformVECREDUCE_ADDCombine()
17333 SDValue Op = N0; in PerformVECREDUCE_ADDCombine()
17341 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, N0->getValueType(0), Mul); in PerformVECREDUCE_ADDCombine()
17342 if (Op != N0) in PerformVECREDUCE_ADDCombine()
17343 Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0), in PerformVECREDUCE_ADDCombine()
17344 N0->getOperand(0), Ext, N0->getOperand(2)); in PerformVECREDUCE_ADDCombine()
17736 SDValue N0 = N->getOperand(0); in PerformShiftCombine() local
17741 ConstantSDNode *AndMaskNode = dyn_cast<ConstantSDNode>(N0->getOperand(1)); in PerformShiftCombine()
17752 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, N0->getOperand(0), in PerformShiftCombine()
17799 SDValue N0 = N->getOperand(0); in PerformSplittingToWideningLoad() local
17800 if (N0.getOpcode() != ISD::LOAD) in PerformSplittingToWideningLoad()
17802 LoadSDNode *LD = cast<LoadSDNode>(N0.getNode()); in PerformSplittingToWideningLoad()
17803 if (!LD->isSimple() || !N0.hasOneUse() || LD->isIndexed() || in PerformSplittingToWideningLoad()
17881 SDValue N0 = N->getOperand(0); in PerformExtendCombine() local
17888 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
17889 SDValue Vec = N0.getOperand(0); in PerformExtendCombine()
17890 SDValue Lane = N0.getOperand(1); in PerformExtendCombine()
17892 EVT EltVT = N0.getValueType(); in PerformExtendCombine()
17977 SDValue N0 = N->getOperand(0); in PerformMinMaxCombine() local
18014 if (IsSignedSaturate(N, N0.getNode())) { in PerformMinMaxCombine()
18030 N0->getOperand(0), DAG.getConstant(0, DL, MVT::i32)); in PerformMinMaxCombine()
18070 DAG.getNode(ARMISD::VQMOVNu, DL, HalfVT, DAG.getUNDEF(HalfVT), N0, in PerformMinMaxCombine()
18711 SDValue N0 = N->getOperand(0); in PerformSplittingMVEEXTToWideningLoad() local
18712 LoadSDNode *LD = dyn_cast<LoadSDNode>(N0.getNode()); in PerformSplittingMVEEXTToWideningLoad()
18713 if (!LD || !LD->isSimple() || !N0.hasOneUse() || LD->isIndexed()) in PerformSplittingMVEEXTToWideningLoad()