Lines Matching refs:N0
613 SDValue N0 = Node->getOperand(0); in tryShrinkShlLogicImm() local
626 SDValue Shift = N0; in tryShrinkShlLogicImm()
632 if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in tryShrinkShlLogicImm()
633 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
635 Shift = N0.getOperand(0); in tryShrinkShlLogicImm()
691 SDValue N0 = Node->getOperand(0); in trySignedBitfieldExtract() local
692 if (!N0.hasOneUse()) in trySignedBitfieldExtract()
695 auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL, in trySignedBitfieldExtract()
697 return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0), in trySignedBitfieldExtract()
708 if (N0.getOpcode() == ISD::SHL) { in trySignedBitfieldExtract()
709 auto *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1)); in trySignedBitfieldExtract()
723 SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT); in trySignedBitfieldExtract()
730 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { in trySignedBitfieldExtract()
732 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in trySignedBitfieldExtract()
741 SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT); in trySignedBitfieldExtract()
1076 SDValue N0 = Node->getOperand(0); in Select() local
1077 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse() || in Select()
1078 !isa<ConstantSDNode>(N0.getOperand(1))) in Select()
1081 uint64_t Mask = N0.getConstantOperandVal(1); in Select()
1091 RISCV::SRLIW, DL, VT, N0->getOperand(0), in Select()
1106 SDValue N0 = Node->getOperand(0); in Select() local
1107 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(N0.getOperand(1))) in Select()
1110 uint64_t Mask = N0.getConstantOperandVal(1); in Select()
1114 if (isShiftedMask_64(Mask) && N0.hasOneUse()) { in Select()
1120 RISCV::SRLIW, DL, VT, N0->getOperand(0), in Select()
1147 N0->getOperand(0), CurDAG->getTargetConstant(ShAmt, DL, VT)); in Select()
1153 if (!N0.hasOneUse()) in Select()
1160 N0->getOperand(0), CurDAG->getTargetConstant(ShAmt, DL, VT)); in Select()
1167 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0), in Select()
1190 SDValue N0 = Node->getOperand(0); in Select() local
1191 if (N0.getOpcode() != ISD::SIGN_EXTEND_INREG || !N0.hasOneUse()) in Select()
1195 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in Select()
1201 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0), in Select()
1223 SDValue N0 = Node->getOperand(0); in Select() local
1238 bool LeftShift = N0.getOpcode() == ISD::SHL; in Select()
1239 if (LeftShift || N0.getOpcode() == ISD::SRL) { in Select()
1240 auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in Select()
1263 bool OneUseOrZExtW = N0.hasOneUse() || C1 == UINT64_C(0xFFFFFFFF); in Select()
1265 SDValue X = N0.getOperand(0); in Select()
1285 if (C2 >= 32 && (Leading - C2) == 1 && N0.hasOneUse() && in Select()
1447 if (tryUnsignedBitfieldExtract(Node, DL, VT, N0, Msb, 0)) in Select()
1469 SDValue N0 = Node->getOperand(0); in Select() local
1470 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(N0.getOperand(1))) in Select()
1473 uint64_t C2 = N0.getConstantOperandVal(1); in Select()
1489 if (IsANDIOrZExt && (isInt<12>(N1C->getSExtValue()) || !N0.hasOneUse())) in Select()
1496 if (IsZExtW && (isInt<32>(N1C->getSExtValue()) || !N0.hasOneUse())) in Select()
1520 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0.getOperand(0), in Select()
2893 SDValue N0 = N.getOperand(0); in selectSExtBits() local
2894 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && in selectSExtBits()
2896 N0.getConstantOperandVal(1) == ShiftAmt) in selectSExtBits()
2897 return N0.getOperand(0); in selectSExtBits()
2935 SDValue N0 = N.getOperand(0); in selectSHXADDOp() local
2937 bool LeftShift = N0.getOpcode() == ISD::SHL; in selectSHXADDOp()
2938 if ((LeftShift || N0.getOpcode() == ISD::SRL) && in selectSHXADDOp()
2939 isa<ConstantSDNode>(N0.getOperand(1))) { in selectSHXADDOp()
2941 unsigned C2 = N0.getConstantOperandVal(1); in selectSHXADDOp()
2959 RISCV::SRLI, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2972 RISCV::SRLI, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2984 SDValue N0 = N.getOperand(0); in selectSHXADDOp() local
2985 if (N0.getOpcode() == ISD::AND && N0.hasOneUse() && in selectSHXADDOp()
2986 isa<ConstantSDNode>(N0.getOperand(1))) { in selectSHXADDOp()
2987 uint64_t Mask = N0.getConstantOperandVal(1); in selectSHXADDOp()
3000 RISCV::SRLIW, DL, VT, N0.getOperand(0), in selectSHXADDOp()
3012 RISCV::SRLIW, DL, VT, N0.getOperand(0), in selectSHXADDOp()
3031 SDValue N0 = N.getOperand(0); in selectSHXADD_UWOp() local
3032 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && in selectSHXADD_UWOp()
3033 N0.hasOneUse()) { in selectSHXADD_UWOp()
3035 unsigned C2 = N0.getConstantOperandVal(1); in selectSHXADD_UWOp()
3049 RISCV::SLLI, DL, VT, N0.getOperand(0), in selectSHXADD_UWOp()
3465 SDValue N0 = N->getOperand(0); in doPeepholeSExtW() local
3466 if (!N0.isMachineOpcode()) in doPeepholeSExtW()
3469 switch (N0.getMachineOpcode()) { in doPeepholeSExtW()
3480 switch (N0.getMachineOpcode()) { in doPeepholeSExtW()
3490 SDValue N00 = N0.getOperand(0); in doPeepholeSExtW()
3491 SDValue N01 = N0.getOperand(1); in doPeepholeSExtW()
3494 if (N0.getMachineOpcode() == RISCV::SLLI && in doPeepholeSExtW()
3514 if (N0.getValueType() == MVT::i32) in doPeepholeSExtW()
3519 ReplaceUses(N, N0.getNode()); in doPeepholeSExtW()