| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopBoundSplit.cpp | 52 ConditionInfo &Cond, const Loop &L) { in analyzeICmp() argument
53 Cond.ICmp = ICmp; in analyzeICmp()
54 if (match(ICmp, m_ICmp(Cond.Pred, m_Value(Cond.AddRecValue), in analyzeICmp()
55 m_Value(Cond.BoundValue)))) { in analyzeICmp()
56 const SCEV *AddRecSCEV = SE.getSCEV(Cond.AddRecValue); in analyzeICmp()
57 const SCEV *BoundSCEV = SE.getSCEV(Cond.BoundValue); in analyzeICmp()
62 std::swap(Cond.AddRecValue, Cond.BoundValue); in analyzeICmp()
64 Cond.Pred = ICmpInst::getSwappedPredicate(Cond.Pred); in analyzeICmp()
67 Cond.AddRecSCEV = dyn_cast<SCEVAddRecExpr>(AddRecSCEV); in analyzeICmp()
68 Cond.BoundSCEV = BoundSCEV; in analyzeICmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 92 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
110 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
111 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
118 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
119 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
161 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
164 if (Cond.empty()) { in insertBranch()
172 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
174 if (Cond[0].getImm()) in insertBranch()
175 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[ in insertBranch()
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| H A D | WebAssemblyLowerBrUnless.cpp | 70 Register Cond = MI.getOperand(1).getReg(); in runOnMachineFunction() local
74 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
75 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
76 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
177 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
192 .addReg(Cond); in runOnMachineFunction()
194 Cond = Tmp; in runOnMachineFunction()
203 .addReg(Cond); in runOnMachineFunction()
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| H A D | WebAssemblyFixBrTableDefaults.cpp | 102 SmallVector<MachineOperand, 2> Cond; in fixBrTableDefault() local
104 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond); in fixBrTableDefault()
119 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info"); in fixBrTableDefault()
128 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 75 const SmallVectorImpl<MachineOperand> &Cond, in guaranteesZeroRegInBlock() argument
77 assert(Cond.size() == 3 && "Unexpected number of operands"); in guaranteesZeroRegInBlock()
79 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in guaranteesZeroRegInBlock()
80 if (CC == RISCVCC::COND_EQ && Cond[2].isReg() && in guaranteesZeroRegInBlock()
81 Cond[2].getReg() == RISCV::X0 && TBB == &MBB) in guaranteesZeroRegInBlock()
83 if (CC == RISCVCC::COND_NE && Cond[2].isReg() && in guaranteesZeroRegInBlock()
84 Cond[2].getReg() == RISCV::X0 && TBB != &MBB) in guaranteesZeroRegInBlock()
101 SmallVector<MachineOperand, 3> Cond; in optimizeBlock() local
102 if (TII->analyzeBranch(*PredMBB, TBB, FBB, Cond, /*AllowModify*/ false) || in optimizeBlock()
103 Cond.empty()) in optimizeBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 74 void shrinkWrapCI(CallInst *CI, Value *Cond);
132 Value *Cond = nullptr; in performCallDomainErrorOnly() local
143 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
154 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
163 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
171 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
177 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
184 Value *Cond = nullptr; in performCallRangeErrorOnly() local
202 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
209 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 133 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
134 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
136 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
160 Cond[0].setImm(CC); in reverseBranchCondition()
167 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
201 Cond.clear(); in analyzeBranch()
225 if (Cond.empty()) { in analyzeBranch()
228 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
234 assert(Cond.size() == 1); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 192 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
274 ArrayRef<MachineOperand> Cond, in insertBranch() argument
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 173 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
350 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
351 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
352 Cond[2].setImm(getOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
372 ArrayRef<MachineOperand> Cond, in insertBranch() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 95 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
113 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
131 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
180 ArrayRef<MachineOperand> Cond, in insertBranch() argument
187 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
192 if (Cond.empty()) // Unconditional branch in insertBranch()
195 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
200 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.cpp | 255 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
262 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
264 Cond.push_back(LastInst.getOperand(i)); in parseCondBranch()
270 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
273 Cond.clear(); in analyzeBranch()
311 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
318 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
385 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
391 assert(Cond.size() <= 3 && Cond.size() != 1 && in insertBranch()
395 if (Cond.empty()) { in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIAnnotateControlFlow.cpp | 84 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
211 Value *Cond = IRB.CreateExtractValue(IfCall, {0}); in openIf() local
213 Term->setCondition(Cond); in openIf()
226 Value *Cond = IRB.CreateExtractValue(ElseCall, {0}); in insertElse() local
228 Term->setCondition(Cond); in insertElse()
235 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
237 auto CreateBreak = [this, Cond, Broken](Instruction *I) -> CallInst * { in handleLoopCondition()
238 return IRBuilder<>(I).CreateCall(IfBreak, {Cond, Broken}); in handleLoopCondition()
241 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
254 if (isa<Constant>(Cond)) { in handleLoopCondition()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 95 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
102 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
105 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
111 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
114 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
121 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
122 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
126 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
127 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
129 MIB.add(Cond[i]); in BuildCondBr()
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| H A D | MipsInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
206 SmallVectorImpl<MachineOperand> &Cond) const;
209 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFAdjustOpt.cpp | 225 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
226 if (!Cond || B2->getFirstNonPHI() != Cond) in serializeICMPCrossBB()
228 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
229 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
235 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
236 if (!Cond) in serializeICMPCrossBB()
238 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
239 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
260 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAsmAlias.td | 53 multiclass CMPCCXADD_Aliases<string Cond, int CC> {
55 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
57 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
60 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
62 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
68 multiclass CCMP_Aliases<string Cond, int CC> {
70 def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",
72 def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",
74 def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",
76 def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",
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| H A D | X86FlagsCopyLowering.cpp | 100 const DebugLoc &TestLoc, X86::CondCode Cond);
103 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
722 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
723 if (Cond != X86::COND_INVALID && !MI.mayStore() && in collectCondsInRegs()
727 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
740 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
743 .addImm(Cond); in promoteCondToReg()
752 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg() argument
753 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
754 unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)]; in getCondOrInverseInReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 267 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
305 Cond.clear(); in analyzeBranch()
329 if (Cond.empty()) { in analyzeBranch()
370 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
376 assert(Cond.size() == 1); in analyzeBranch()
385 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
400 ArrayRef<MachineOperand> Cond, in insertBranch() argument
407 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
410 if (Cond.empty()) { in insertBranch()
420 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | GuardUtils.cpp | 75 auto *Cond = BI->getCondition(); in parseWidenableBranch()
76 if (!Cond->hasOneUse()) in parseWidenableBranch()
82 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
94 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
96 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
73 auto *Cond = BI->getCondition(); parseWidenableBranch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1669 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition() local
1671 DAG.getConstant(Cond, DL, MVT::i8), BTST); in getBitTestCondition()
2213 SDValue Cond = Op.getOperand(3); in LowerSETCCCARRY() local
2217 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get()); in LowerSETCCCARRY()
2262 SDValue Cond = Op.getOperand(0); in LowerSELECT() local
2268 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2269 if (SDValue NewCond = LowerSETCC(Cond, DAG)) in LowerSELECT()
2270 Cond = NewCond; in LowerSELECT()
2277 if (Cond.getOpcode() == M68kISD::SETCC && in LowerSELECT()
2278 Cond.getOperand(1).getOpcode() == M68kISD::CMP && in LowerSELECT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.cpp | 36 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
41 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
42 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
48 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
51 Cond.clear(); in analyzeBranch()
97 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
104 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
156 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
162 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
166 if (Cond.empty()) { in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUAsmUtils.h | 31 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
40 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
52 return !Cond || Cond(STI); in isSupported()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 193 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
199 Cond.push_back(MachineOperand::CreateImm(Opc)); in parseCondBranch()
200 Cond.push_back(MachineOperand::CreateImm(CC)); in parseCondBranch()
206 Cond.push_back(MachineOperand::CreateReg(Reg, false)); in parseCondBranch()
247 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
268 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
302 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
330 ArrayRef<MachineOperand> Cond, in insertBranch() argument
334 assert((Cond.size() <= 3) && in insertBranch()
337 if (Cond.empty()) { in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 138 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); in parseCondBranch()
140 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
141 Cond.push_back(LastInst->getOperand(2)); in parseCondBranch()
147 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
168 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
201 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
229 ArrayRef<MachineOperand> Cond, in insertBranch() argument
232 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
235 if (Cond.empty()) { in insertBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 439 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
443 Cond.clear(); in analyzeBranch()
534 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
535 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
540 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
541 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
547 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
548 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
549 Cond.push_back(LastInst->getOperand(1)); in analyzeBranch()
564 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in analyzeBranch()
[all …]
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