Home
last modified time | relevance | path

Searched refs:Cond (Results 1 – 25 of 379) sorted by relevance

12345678910>>...16

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopBoundSplit.cpp52 ConditionInfo &Cond, const Loop &L) { in analyzeICmp() argument
53 Cond.ICmp = ICmp; in analyzeICmp()
54 if (match(ICmp, m_ICmp(Cond.Pred, m_Value(Cond.AddRecValue), in analyzeICmp()
55 m_Value(Cond.BoundValue)))) { in analyzeICmp()
56 const SCEV *AddRecSCEV = SE.getSCEV(Cond.AddRecValue); in analyzeICmp()
57 const SCEV *BoundSCEV = SE.getSCEV(Cond.BoundValue); in analyzeICmp()
62 std::swap(Cond.AddRecValue, Cond.BoundValue); in analyzeICmp()
64 Cond.Pred = ICmpInst::getSwappedPredicate(Cond.Pred); in analyzeICmp()
67 Cond.AddRecSCEV = dyn_cast<SCEVAddRecExpr>(AddRecSCEV); in analyzeICmp()
68 Cond.BoundSCEV = BoundSCEV; in analyzeICmp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.cpp212 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
213 assert(Cond.size() <= 4 && "Invalid branch condition!"); in reverseBranchCondition()
215 switch (Cond[0].getImm()) { in reverseBranchCondition()
217 Cond[0].setImm(Xtensa::BNE); in reverseBranchCondition()
220 Cond[0].setImm(Xtensa::BEQ); in reverseBranchCondition()
223 Cond[0].setImm(Xtensa::BGE); in reverseBranchCondition()
226 Cond[0].setImm(Xtensa::BLT); in reverseBranchCondition()
229 Cond[0].setImm(Xtensa::BGEU); in reverseBranchCondition()
232 Cond[0].setImm(Xtensa::BLTU); in reverseBranchCondition()
235 Cond[0].setImm(Xtensa::BNEI); in reverseBranchCondition()
[all …]
H A DXtensaInstrInfo.h79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
88 SmallVectorImpl<MachineOperand> &Cond,
95 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
107 ArrayRef<MachineOperand> Cond, const DebugLoc &DL,
112 ArrayRef<MachineOperand> Cond, DebugLoc DL,
121 SmallVectorImpl<MachineOperand> &Cond,
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp26 DefinedSVal Cond, in assumeInternal() argument
29 if (std::optional<Loc> LV = Cond.getAs<Loc>()) { in assumeInternal()
38 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assumeInternal()
41 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assumeInternal()
45 NonLoc Cond, bool Assumption) { in assume() argument
46 State = assumeAux(State, Cond, Assumption); in assume()
48 return EE->processAssume(State, Cond, Assumption); in assume()
53 NonLoc Cond, in assumeAux() argument
58 if (!canReasonAbout(Cond)) { in assumeAux()
60 SymbolRef Sym = Cond.getAsSymbol(); in assumeAux()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp94 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
112 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
113 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
120 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
121 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
163 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
166 if (Cond.empty()) { in insertBranch()
174 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
176 if (Cond[0].getImm()) in insertBranch()
177 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
[all …]
H A DWebAssemblyLowerBrUnless.cpp70 Register Cond = MI.getOperand(1).getReg(); in runOnMachineFunction() local
74 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
75 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
76 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
177 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
192 .addReg(Cond); in runOnMachineFunction()
194 Cond = Tmp; in runOnMachineFunction()
203 .addReg(Cond); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp71 const SmallVectorImpl<MachineOperand> &Cond, in guaranteesZeroRegInBlock() argument
73 assert(Cond.size() == 3 && "Unexpected number of operands"); in guaranteesZeroRegInBlock()
75 auto Opc = Cond[0].getImm(); in guaranteesZeroRegInBlock()
76 if (Opc == RISCV::BEQ && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
79 if (Opc == RISCV::BNE && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
97 SmallVector<MachineOperand, 3> Cond; in optimizeBlock() local
98 if (TII->analyzeBranch(*PredMBB, TBB, FBB, Cond, /*AllowModify*/ false) || in optimizeBlock()
99 Cond.empty()) in optimizeBlock()
103 if (!guaranteesZeroRegInBlock(MBB, Cond, TBB)) in optimizeBlock()
106 Register TargetReg = Cond[1].getReg(); in optimizeBlock()
H A DRISCVLateBranchOpt.cpp50 SmallVector<MachineOperand, 4> Cond; in runOnBasicBlock() local
51 if (RII->analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false)) in runOnBasicBlock()
54 if (!TBB || Cond.size() != 3) in runOnBasicBlock()
57 RISCVCC::CondCode CC = RISCVInstrInfo::getCondFromBranchOpc(Cond[0].getImm()); in runOnBasicBlock()
65 if (!RISCVInstrInfo::isFromLoadImm(MRI, Cond[1], C0) || in runOnBasicBlock()
66 !RISCVInstrInfo::isFromLoadImm(MRI, Cond[2], C1)) in runOnBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp74 void shrinkWrapCI(CallInst *CI, Value *Cond);
132 Value *Cond = nullptr; in performCallDomainErrorOnly() local
143 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
154 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
163 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
171 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
177 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
184 Value *Cond = nullptr; in performCallRangeErrorOnly() local
202 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
209 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp128 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
129 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
131 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
155 Cond[0].setImm(CC); in reverseBranchCondition()
162 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
196 Cond.clear(); in analyzeBranch()
220 if (Cond.empty()) { in analyzeBranch()
223 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
229 assert(Cond.size() == 1); in analyzeBranch()
237 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp188 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
216 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
217 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
238 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
270 ArrayRef<MachineOperand> Cond, in insertBranch() argument
275 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
280 if (Cond.empty()) { in insertBranch()
285 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
286 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp85 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
103 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
121 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
170 ArrayRef<MachineOperand> Cond, in insertBranch() argument
177 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
182 if (Cond.empty()) // Unconditional branch in insertBranch()
185 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
190 BuildMI(&MBB, DL, get(NVPTX::CBranch)).add(Cond[0]).addMBB(TBB); in insertBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp173 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
353 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
354 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
355 Cond[2].setImm(getOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
375 ArrayRef<MachineOperand> Cond, in insertBranch() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAsmAlias.td53 multiclass CMPCCXADD_Aliases<string Cond, int CC> {
55 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
57 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
60 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
62 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
68 multiclass CCMP_Aliases<string Cond, int CC> {
70 def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",
72 def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",
74 def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",
76 def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIAnnotateControlFlow.cpp86 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
192 Value *Cond = IRB.CreateExtractValue(IfCall, {0}); in openIf() local
194 Term->setCondition(Cond); in openIf()
208 Value *Cond = IRB.CreateExtractValue(ElseCall, {0}); in insertElse() local
210 Term->setCondition(Cond); in insertElse()
217 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
219 auto CreateBreak = [this, Cond, Broken](Instruction *I) -> CallInst * { in handleLoopCondition()
221 getDecl(IfBreak, Intrinsic::amdgcn_if_break, IntMask), {Cond, Broken}); in handleLoopCondition()
224 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
242 if (isa<Constant>(Cond)) { in handleLoopCondition()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFAdjustOpt.cpp224 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
225 if (!Cond || &*B2->getFirstNonPHIIt() != Cond) in serializeICMPCrossBB()
227 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
228 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
234 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
235 if (!Cond) in serializeICMPCrossBB()
237 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
238 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
259 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp104 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
111 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
114 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
120 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
123 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
130 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
131 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
135 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
136 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
138 MIB.add(Cond[i]); in BuildCondBr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp264 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
302 Cond.clear(); in analyzeBranch()
326 if (Cond.empty()) { in analyzeBranch()
367 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
373 assert(Cond.size() == 1); in analyzeBranch()
382 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
397 ArrayRef<MachineOperand> Cond, in insertBranch() argument
404 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
407 if (Cond.empty()) { in insertBranch()
417 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DGuardUtils.cpp75 auto *Cond = BI->getCondition(); in parseWidenableBranch()
76 if (!Cond->hasOneUse()) in parseWidenableBranch()
82 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
94 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
96 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
73 auto *Cond = BI->getCondition(); parseWidenableBranch() local
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1671 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition() local
1673 DAG.getConstant(Cond, DL, MVT::i8), BTST); in getBitTestCondition()
2215 SDValue Cond = Op.getOperand(3); in LowerSETCCCARRY() local
2219 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get()); in LowerSETCCCARRY()
2264 SDValue Cond = Op.getOperand(0); in LowerSELECT() local
2270 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2271 if (SDValue NewCond = LowerSETCC(Cond, DAG)) in LowerSELECT()
2272 Cond = NewCond; in LowerSELECT()
2279 if (Cond.getOpcode() == M68kISD::SETCC && in LowerSELECT()
2280 Cond.getOperand(1).getOpcode() == M68kISD::CMP && in LowerSELECT()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DBasicBlockUtils.h426 SplitBlockAndInsertIfThen(Value *Cond, BasicBlock::iterator SplitBefore,
431 inline Instruction *SplitBlockAndInsertIfThen(Value *Cond, Instruction *SplitBefore,
437 return SplitBlockAndInsertIfThen(Cond, SplitBefore->getIterator(),
445 SplitBlockAndInsertIfElse(Value *Cond, BasicBlock::iterator SplitBefore,
450 inline Instruction *SplitBlockAndInsertIfElse(Value *Cond, Instruction *SplitBefore,
456 return SplitBlockAndInsertIfElse(Cond, SplitBefore->getIterator(),
478 Value *Cond, BasicBlock::iterator SplitBefore, Instruction **ThenTerm,
482 inline void SplitBlockAndInsertIfThenElse(Value *Cond, Instruction *SplitBefore,
489 SplitBlockAndInsertIfThenElse(Cond, SplitBefore->getIterator(), ThenTerm,
521 Value *Cond, BasicBlock::iterator SplitBefore, BasicBlock **ThenBlock,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp286 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
293 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
295 Cond.push_back(LastInst.getOperand(i)); in parseCondBranch()
301 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
304 Cond.clear(); in analyzeBranch()
342 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
349 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
581 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
587 assert(Cond.size() <= 3 && Cond.size() != 1 && in insertBranch()
591 if (Cond.empty()) { in insertBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp36 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
41 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
42 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
48 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
51 Cond.clear(); in analyzeBranch()
97 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
104 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
156 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
162 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
166 if (Cond.empty()) { in insertBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUAsmUtils.h31 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
40 bool (*Cond)(const MCSubtargetInfo &STI) = nullptr; member
52 return !Cond || Cond(STI); in isSupported()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp191 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
197 Cond.push_back(MachineOperand::CreateImm(Opc)); in parseCondBranch()
198 Cond.push_back(MachineOperand::CreateImm(CC)); in parseCondBranch()
204 Cond.push_back(MachineOperand::CreateReg(Reg, false)); in parseCondBranch()
245 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
266 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
300 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
328 ArrayRef<MachineOperand> Cond, in insertBranch() argument
332 assert((Cond.size() <= 3) && in insertBranch()
335 if (Cond.empty()) { in insertBranch()
[all …]

12345678910>>...16