Lines Matching refs:Cond
193 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
199 Cond.push_back(MachineOperand::CreateImm(Opc)); in parseCondBranch()
200 Cond.push_back(MachineOperand::CreateImm(CC)); in parseCondBranch()
206 Cond.push_back(MachineOperand::CreateReg(Reg, false)); in parseCondBranch()
247 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
268 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
302 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
330 ArrayRef<MachineOperand> Cond, in insertBranch() argument
334 assert((Cond.size() <= 3) && in insertBranch()
337 if (Cond.empty()) { in insertBranch()
346 unsigned Opc = Cond[0].getImm(); in insertBranch()
347 unsigned CC = Cond[1].getImm(); in insertBranch()
349 Register Reg = Cond[2].getReg(); in insertBranch()
394 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
395 assert(Cond.size() <= 3); in reverseBranchCondition()
396 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm()); in reverseBranchCondition()
397 Cond[1].setImm(GetOppositeBranchCondition(CC)); in reverseBranchCondition()