439                                      SmallVectorImpl<MachineOperand> &Cond,  in analyzeBranch()  argument
443   Cond.clear();  in analyzeBranch()
534       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));  in analyzeBranch()
535       Cond.push_back(LastInst->getOperand(0));  in analyzeBranch()
540       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));  in analyzeBranch()
541       Cond.push_back(LastInst->getOperand(0));  in analyzeBranch()
547       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));  in analyzeBranch()
548       Cond.push_back(LastInst->getOperand(0));  in analyzeBranch()
549       Cond.push_back(LastInst->getOperand(1));  in analyzeBranch()
564     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));  in analyzeBranch()
565     Cond.push_back(SecondLastInst->getOperand(0));  in analyzeBranch()
575     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));  in analyzeBranch()
576     Cond.push_back(SecondLastInst->getOperand(0));  in analyzeBranch()
577     Cond.push_back(SecondLastInst->getOperand(1));  in analyzeBranch()
595     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));  in analyzeBranch()
596     Cond.push_back(SecondLastInst->getOperand(0));  in analyzeBranch()
632                                         ArrayRef<MachineOperand> Cond,  in insertBranch()  argument
637   assert(validateBranchCond(Cond) && "Invalid branching condition");  in insertBranch()
644   if (!Cond.empty() && Cond[0].isImm())  in insertBranch()
645     BccOpc = Cond[0].getImm();  in insertBranch()
648     if (Cond.empty()) {  in insertBranch()
654       SmallVector<MachineOperand, 4> Cond;  in insertBranch()  local
657           !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&  in insertBranch()
659         reverseBranchCondition(Cond);  in insertBranch()
661         return insertBranch(MBB, TBB, nullptr, Cond, DL);  in insertBranch()
664     } else if (isEndLoopN(Cond[0].getImm())) {  in insertBranch()
665       int EndLoopOp = Cond[0].getImm();  in insertBranch()
666       assert(Cond[1].isMBB());  in insertBranch()
670       MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),  in insertBranch()
676     } else if (isNewValueJump(Cond[0].getImm())) {  in insertBranch()
677       assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");  in insertBranch()
681       unsigned Flags1 = getUndefRegState(Cond[1].isUndef());  in insertBranch()
684       if (Cond[2].isReg()) {  in insertBranch()
685         unsigned Flags2 = getUndefRegState(Cond[2].isUndef());  in insertBranch()
686         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).  in insertBranch()
687           addReg(Cond[2].getReg(), Flags2).addMBB(TBB);  in insertBranch()
688       } else if(Cond[2].isImm()) {  in insertBranch()
689         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).  in insertBranch()
690           addImm(Cond[2].getImm()).addMBB(TBB);  in insertBranch()
694       assert((Cond.size() == 2) && "Malformed cond vector");  in insertBranch()
695       const MachineOperand &RO = Cond[1];  in insertBranch()
701   assert((!Cond.empty()) &&  in insertBranch()
703   assert((!isNewValueJump(Cond[0].getImm())) &&  in insertBranch()
706   if (isEndLoopN(Cond[0].getImm())) {  in insertBranch()
707     int EndLoopOp = Cond[0].getImm();  in insertBranch()
708     assert(Cond[1].isMBB());  in insertBranch()
712     MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),  in insertBranch()
719     const MachineOperand &RO = Cond[1];  in insertBranch()
758       SmallVectorImpl<MachineOperand> &Cond) override {  in createTripCountGreaterCondition()  argument
766       Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));  in createTripCountGreaterCondition()
767       Cond.push_back(NewCmp->getOperand(0));  in createTripCountGreaterCondition()
1635       SmallVectorImpl<MachineOperand> &Cond) const {  in reverseBranchCondition()
1636   if (Cond.empty())  in reverseBranchCondition()
1638   assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");  in reverseBranchCondition()
1639   unsigned opcode = Cond[0].getImm();  in reverseBranchCondition()
1645   Cond[0].setImm(NewOpcode);  in reverseBranchCondition()
1673     MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {  in PredicateInstruction()
1674   if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||  in PredicateInstruction()
1675       isEndLoopN(Cond[0].getImm())) {  in PredicateInstruction()
1681   bool invertJump = predOpcodeHasNot(Cond);  in PredicateInstruction()
1703   bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);  in PredicateInstruction()
3275 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {  in predOpcodeHasNot()
3276   if (Cond.empty() || !isPredicated(Cond[0].getImm()))  in predOpcodeHasNot()
3278   return !isPredicatedTrue(Cond[0].getImm());  in predOpcodeHasNot()
4372       SmallVectorImpl<MachineOperand> &Cond) const {  in getInvertedPredSense()
4373   if (Cond.empty())  in getInvertedPredSense()
4375   unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());  in getInvertedPredSense()
4376   Cond[0].setImm(Opc);  in getInvertedPredSense()
4549 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,  in getPredReg()  argument
4551   if (Cond.empty())  in getPredReg()
4553   assert(Cond.size() == 2);  in getPredReg()
4554   if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {  in getPredReg()
4558   PredReg = Cond[1].getReg();  in getPredReg()
4562   if (Cond[1].isImplicit())  in getPredReg()
4564   if (Cond[1].isUndef())  in getPredReg()
4716 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)  in validateBranchCond()
4718   return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));  in validateBranchCond()