Lines Matching refs:Cond
138 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); in parseCondBranch()
140 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
141 Cond.push_back(LastInst->getOperand(2)); in parseCondBranch()
147 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
168 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
201 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
229 ArrayRef<MachineOperand> Cond, in insertBranch() argument
232 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
235 if (Cond.empty()) { in insertBranch()
245 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); in insertBranch()
251 Register Reg = Cond[2].getReg(); in insertBranch()
252 if (IsIntegerCC(Cond[0].getImm())) { in insertBranch()
269 if (Cond[1].isImm()) { in insertBranch()
271 .add(Cond[0]) // condition code in insertBranch()
272 .add(Cond[1]) // lhs in insertBranch()
273 .add(Cond[2]) // rhs in insertBranch()
277 .add(Cond[0]) in insertBranch()
278 .add(Cond[1]) in insertBranch()
279 .add(Cond[2]) in insertBranch()
315 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
316 VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm()); in reverseBranchCondition()
317 Cond[0].setImm(GetOppositeBranchCondition(CC)); in reverseBranchCondition()