Lines Matching refs:Cond
95 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
102 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
105 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
111 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
114 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
121 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
122 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
126 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
127 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
129 MIB.add(Cond[i]); in BuildCondBr()
137 ArrayRef<MachineOperand> Cond, in insertBranch() argument
149 assert((Cond.size() <= 3) && in insertBranch()
154 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
161 if (Cond.empty()) in insertBranch()
164 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
197 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
198 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
200 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); in reverseBranchCondition()
206 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, in analyzeBranch() argument
257 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in analyzeBranch()
286 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in analyzeBranch()