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Searched refs:CSR_READ_4 (Results 1 – 25 of 53) sorted by relevance

123

/freebsd/sys/dev/bge/
H A Dif_bge.c623 CSR_READ_4(sc, off); in bge_writembx()
965 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
973 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
980 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
992 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
1001 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
1057 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
1067 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1118 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1121 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
[all …]
/freebsd/sys/dev/et/
H A Dif_et.c429 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
443 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
474 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
529 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
531 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
534 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
578 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
651 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( in et_stop()
1178 status = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1473 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { in et_stop_rxdma()
[all …]
/freebsd/sys/dev/dc/
H A Ddcphy.c75 CSR_READ_4(sc, reg) | x)
79 CSR_READ_4(sc, reg) & ~x)
206 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
261 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
307 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
311 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
364 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
368 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
H A Dif_dc.c357 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
360 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
371 CSR_READ_4(sc, DC_BUSCTL); in dc_delay()
407 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { in dc_eeprom_width()
519 r = CSR_READ_4(sc, DC_SIO); in dc_eeprom_getword_pnic()
540 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; in dc_eeprom_getword_xircom()
543 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; in dc_eeprom_getword_xircom()
581 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) in dc_eeprom_getword()
644 val = CSR_READ_4(sc, DC_SIO); in dc_mii_bitbang_read()
688 rval = CSR_READ_4(sc, DC_PN_MII); in dc_miibus_readreg()
[all …]
H A Dpnphy.c207 reg = CSR_READ_4(dc_sc, DC_ISR); in pnphy_status()
210 reg = CSR_READ_4(dc_sc, DC_NETCFG); in pnphy_status()
/freebsd/sys/dev/alc/
H A Dif_alc.c307 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
334 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
372 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
398 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
449 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
493 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
524 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
707 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
/freebsd/sys/dev/nge/
H A Dif_nge.c246 CSR_READ_4(sc, reg) | (x))
250 CSR_READ_4(sc, reg) & ~(x))
253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
264 CSR_READ_4(sc, NGE_CSR); in nge_delay()
348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) in nge_eeprom_getword()
388 val = CSR_READ_4(sc, NGE_MEAR); in nge_mii_bitbang_read()
428 reg = CSR_READ_4(sc, NGE_TBI_BMSR); in nge_miibus_readreg()
454 return (CSR_READ_4(sc, reg)); in nge_miibus_readreg()
588 reg = CSR_READ_4(sc, NGE_CFG); in nge_miibus_statchg()
[all …]
/freebsd/sys/dev/bfe/
H A Dif_bfe.c664 val = CSR_READ_4(sc, BFE_TX_CTRL); in bfe_miibus_statchg()
669 flow = CSR_READ_4(sc, BFE_RXCONF); in bfe_miibus_statchg()
679 flow = CSR_READ_4(sc, BFE_MAC_FLOW); in bfe_miibus_statchg()
859 val = CSR_READ_4(sc, BFE_SBINTVEC); in bfe_pci_setup()
863 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); in bfe_pci_setup()
879 CSR_READ_4(sc, reg); in bfe_clear_stats()
881 CSR_READ_4(sc, reg); in bfe_clear_stats()
905 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
926 val = CSR_READ_4(sc, BFE_SBTMSLOW) & in bfe_chip_reset()
934 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) in bfe_chip_reset()
[all …]
H A Dif_bfereg.h444 #define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg) macro
449 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
452 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
/freebsd/sys/dev/jme/
H A Dif_jme.c228 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_readreg()
260 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_writereg()
356 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
371 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
381 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
489 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
490 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
708 reg = CSR_READ_4(sc, JME_CHIPMODE); in jme_attach()
751 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_attach()
767 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
[all …]
/freebsd/sys/dev/sis/
H A Dif_sis.c120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) macro
196 CSR_READ_4(sc, reg) | (x))
200 CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
229 CSR_READ_4(sc, SIS_CSR); in sis_delay()
313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) in sis_eeprom_getword()
415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_read_mac()
416 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
446 val = CSR_READ_4(sc, SIS_EECTL); in sis_mii_bitbang_read()
[all …]
/freebsd/sys/dev/bwi/
H A Dbwimac.c198 return CSR_READ_4(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
247 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */ in bwi_mac_lateattach()
462 state_lo = CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
468 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
474 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
479 status = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_reset()
569 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_test()
576 val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_test()
718 CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */ in bwi_mac_dummy_xmit()
1054 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_fw_load()
[all …]
H A Dif_bwi.c754 val = CSR_READ_4(sc, BWI_ID_HI); in bwi_regwin_info()
788 info = CSR_READ_4(sc, BWI_INFO); in bwi_bbp_attach()
793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); in bwi_bbp_attach()
920 val = CSR_READ_4(sc, BWI_FLAGS); in bwi_bus_init()
977 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ in bwi_bus_init()
979 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ in bwi_bus_init()
1066 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); in bwi_get_clock_freq()
1079 val = CSR_READ_4(sc, BWI_CLOCK_INFO); in bwi_get_clock_freq()
1127 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); in bwi_set_clock_mode()
1250 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & in bwi_init_statechg()
[all …]
H A Dif_bwivar.h76 #define CSR_READ_4(sc, reg) \ macro
87 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
92 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
97 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
/freebsd/sys/dev/stge/
H A Dif_stge.c516 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
988 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); in stge_setwol()
1046 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
1379 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_link_task()
1385 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link_task()
1390 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stge_link_task()
1406 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1428 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | in stge_tx_error()
1863 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1865 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); in stge_stats_update()
[all …]
/freebsd/sys/dev/ale/
H A Dif_ale.c213 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
240 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
290 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
391 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
392 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]
/freebsd/sys/dev/lge/
H A Dif_lge.c196 CSR_READ_4(sc, reg) | (x))
200 CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
221 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) in lge_eeprom_getword()
229 val = CSR_READ_4(sc, LGE_EEDATA); in lge_eeprom_getword()
279 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_readreg()
287 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); in lge_miibus_readreg()
302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_writereg()
405 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) in lge_reset()
[all …]
/freebsd/sys/dev/age/
H A Dif_age.c219 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
249 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
340 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); in age_get_macaddr()
369 ea[0] = CSR_READ_4(sc, AGE_PAR0); in age_get_macaddr()
370 ea[1] = CSR_READ_4(sc, AGE_PAR1); in age_get_macaddr()
496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> in age_attach()
520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), in age_attach()
521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); in age_attach()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgevar.h224 #define CSR_READ_4(sc, reg) \ macro
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/freebsd/sys/dev/my/
H A Dif_my.c140 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
141 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
175 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_send_cmd_to_phy()
239 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_phy_readreg()
327 rxfilt = CSR_READ_4(sc, MY_TCRRCR); in my_setmulti()
714 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { in my_setcfg()
719 if (!(CSR_READ_4(sc, MY_TCRRCR) & in my_setcfg()
751 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) in my_reset()
1194 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { in my_txeof()
1215 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { in my_txeof()
[all …]
/freebsd/sys/dev/ipw/
H A Dif_ipw.c1251 r = CSR_READ_4(sc, IPW_CSR_RX_READ); in ipw_rx_intr()
1344 r = CSR_READ_4(sc, IPW_CSR_TX_READ); in ipw_tx_intr()
1381 r = CSR_READ_4(sc, IPW_CSR_INTR); in ipw_intr()
1804 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) in ipw_stop_master()
1811 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_stop_master()
1827 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1832 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) in ipw_reset()
1839 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_reset()
1844 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1986 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_load_firmware()
[all …]
H A Dif_ipwreg.h332 #define CSR_READ_4(sc, reg) \ macro
357 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA))
/freebsd/sys/dev/ti/
H A Dif_ti.c314 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; in ti_eeprom_putbyte()
339 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
348 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
356 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
368 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
379 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) in ti_eeprom_getbyte()
551 origwin = CSR_READ_4(sc, TI_WINBASE); in ti_copy_mem()
730 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); in ti_copy_scratch()
1973 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); in ti_setmulti()
1996 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { in ti_64bitslot_war()
[all …]
/freebsd/sys/dev/iwi/
H A Dif_iwi.c258 return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA); in MEM_READ_4()
931 iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE))); in iwi_media_status()
1570 hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX); in iwi_rx_intr()
1612 hw = CSR_READ_4(sc, txq->csr_ridx); in iwi_tx_intr()
1664 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) { in iwi_intr()
2084 if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED) in iwi_stop_master()
2091 tmp = CSR_READ_4(sc, IWI_CSR_RST); in iwi_stop_master()
2105 tmp = CSR_READ_4(sc, IWI_CSR_CTL); in iwi_reset()
2112 if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY) in iwi_reset()
2122 tmp = CSR_READ_4(sc, IWI_CSR_RST); in iwi_reset()
[all …]
/freebsd/sys/dev/sge/
H A Dif_sge.c184 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg) macro
219 val = CSR_READ_4(sc, ROMInterface); in sge_read_eeprom()
340 val = CSR_READ_4(sc, GMIIControl); in sge_miibus_readreg()
365 val = CSR_READ_4(sc, GMIIControl); in sge_miibus_writereg()
415 ctl = CSR_READ_4(sc, StationControl); in sge_miibus_statchg()
512 CSR_READ_4(sc, IntrControl); in sge_reset()
1330 status = CSR_READ_4(sc, IntrStatus); in sge_intr()
1361 status = CSR_READ_4(sc, IntrStatus); in sge_intr()
1882 CSR_READ_4(sc, IntrMask); in sge_stop()

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