664 	val = CSR_READ_4(sc, BFE_TX_CTRL);  in bfe_miibus_statchg()
669 		flow = CSR_READ_4(sc, BFE_RXCONF);  in bfe_miibus_statchg()
679 		flow = CSR_READ_4(sc, BFE_MAC_FLOW);  in bfe_miibus_statchg()
859 	val = CSR_READ_4(sc, BFE_SBINTVEC);  in bfe_pci_setup()
863 	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);  in bfe_pci_setup()
879 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
881 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
905 	CSR_READ_4(sc, BFE_IMASK);  in bfe_chip_halt()
926 	val = CSR_READ_4(sc, BFE_SBTMSLOW) &  in bfe_chip_reset()
934 		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)  in bfe_chip_reset()
953 	val = CSR_READ_4(sc, BFE_DEVCTRL);  in bfe_chip_reset()
956 	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {  in bfe_chip_reset()
1001 	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)  in bfe_core_disable()
1013 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_disable()
1030 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1034 	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)  in bfe_core_reset()
1036 	val = CSR_READ_4(sc, BFE_SBIMSTATE);  in bfe_core_reset()
1042 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1047 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1088 	val = CSR_READ_4(sc, BFE_RXCONF);  in bfe_set_rx_mode()
1153 		ptr[i/2] = CSR_READ_4(sc, 4096 + i);  in bfe_read_eeprom()
1163 		u_int32_t val = CSR_READ_4(sc, reg);  in bfe_wait_bit()
1193 	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;  in bfe_readphy()
1249 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1251 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1335 	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;  in bfe_txeof()
1380 	status = CSR_READ_4(sc, BFE_DMARX_STAT);  in bfe_rxeof()
1444 	istat = CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()
1453 	CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()