228 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)  in jme_miibus_readreg()
260 		if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)  in jme_miibus_writereg()
356 		reg = CSR_READ_4(sc, JME_SMBCSR);  in jme_eeprom_read_byte()
371 		reg = CSR_READ_4(sc, JME_SMBINTF);  in jme_eeprom_read_byte()
381 	reg = CSR_READ_4(sc, JME_SMBINTF);  in jme_eeprom_read_byte()
489 	par0 = CSR_READ_4(sc, JME_PAR0);  in jme_reg_macaddr()
490 	par1 = CSR_READ_4(sc, JME_PAR1);  in jme_reg_macaddr()
708 	reg = CSR_READ_4(sc, JME_CHIPMODE);  in jme_attach()
751 		reg = CSR_READ_4(sc, JME_SMBCSR);  in jme_attach()
767 		sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &  in jme_attach()
1570 			CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &  in jme_setwol()
1575 			    CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);  in jme_setwol()
1582 	gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;  in jme_setwol()
1583 	pmcs = CSR_READ_4(sc, JME_PMCS);  in jme_setwol()
1598 		CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &  in jme_setwol()
2025 			reg = CSR_READ_4(sc, JME_RXMAC);  in jme_ioctl()
2082 	rxmac = CSR_READ_4(sc, JME_RXMAC);  in jme_mac_config()
2084 	txmac = CSR_READ_4(sc, JME_TXMAC);  in jme_mac_config()
2086 	txpause = CSR_READ_4(sc, JME_TXPFC);  in jme_mac_config()
2099 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &  in jme_mac_config()
2105 		CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |  in jme_mac_config()
2135 		gpreg = CSR_READ_4(sc, JME_GPREG1);  in jme_mac_config()
2287 			    CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);  in jme_link_task()
2290 			    CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);  in jme_link_task()
2312 	status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);  in jme_intr()
2334 	status = CSR_READ_4(sc, JME_INTR_STATUS);  in jme_int_task()
2372 	if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {  in jme_int_task()
2681 	CSR_READ_4(sc, JME_GHC);  in jme_reset()
2692 		gpreg = CSR_READ_4(sc, JME_GPREG1);  in jme_reset()
2694 		gpreg = CSR_READ_4(sc, JME_GPREG1);  in jme_reset()
2697 		ghc = CSR_READ_4(sc, JME_GHC);  in jme_reset()
2703 		CSR_READ_4(sc, JME_GPREG1);  in jme_reset()
2710 	CSR_READ_4(sc, JME_GHC);  in jme_reset()
2848 	reg = CSR_READ_4(sc, JME_PMCS);  in jme_init_locked()
2852 	reg = CSR_READ_4(sc, JME_RXMAC);  in jme_init_locked()
2864 	reg = CSR_READ_4(sc, JME_GPREG0);  in jme_init_locked()
2991 	    CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);  in jme_stop()
3039 	reg = CSR_READ_4(sc, JME_TXCSR);  in jme_stop_tx()
3046 		if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)  in jme_stop_tx()
3059 	reg = CSR_READ_4(sc, JME_RXCSR);  in jme_stop_rx()
3066 		if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)  in jme_stop_rx()
3194 	reg = CSR_READ_4(sc, JME_RXMAC);  in jme_set_vlan()
3228 	rxcfg = CSR_READ_4(sc, JME_RXMAC);  in jme_set_filter()
3275 	CSR_READ_4(sc, JME_STATCSR);  in jme_stats_clear()
3305 	stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);  in jme_stats_update()
3306 	stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);  in jme_stats_update()
3307 	reg = CSR_READ_4(sc, JME_STAT_CRCMII);  in jme_stats_update()
3312 	reg = CSR_READ_4(sc, JME_STAT_RXERR);  in jme_stats_update()
3317 	reg = CSR_READ_4(sc, JME_STAT_FAIL);  in jme_stats_update()
3339 		reg = CSR_READ_4(sc, JME_PHYPOWDN);  in jme_phy_down()
3359 		reg = CSR_READ_4(sc, JME_PHYPOWDN);  in jme_phy_up()