246 		CSR_READ_4(sc, reg) | (x))
250 		CSR_READ_4(sc, reg) & ~(x))
253 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
256 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
264 		CSR_READ_4(sc, NGE_CSR);  in nge_delay()
348 		if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)  in nge_eeprom_getword()
388 	val = CSR_READ_4(sc, NGE_MEAR);  in nge_mii_bitbang_read()
428 			reg = CSR_READ_4(sc, NGE_TBI_BMSR);  in nge_miibus_readreg()
454 		return (CSR_READ_4(sc, reg));  in nge_miibus_readreg()
588 		reg = CSR_READ_4(sc, NGE_CFG);  in nge_miibus_statchg()
603 		reg = CSR_READ_4(sc, NGE_CSR);  in nge_miibus_statchg()
610 			status = CSR_READ_4(sc, NGE_ISR);  in nge_miibus_statchg()
641 		reg = CSR_READ_4(sc, NGE_CSR);  in nge_miibus_statchg()
645 			if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0)  in nge_miibus_statchg()
657 		    CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);  in nge_miibus_statchg()
692 	rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL);  in nge_rxfilter()
757 		if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))  in nge_reset()
783 	v = CSR_READ_4(sc, NGE_CFG);  in nge_reset()
922 	if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) {  in nge_attach()
926 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)  in nge_attach()
1697 	    CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF;  in nge_stats_update()
1699 	    CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF;  in nge_stats_update()
1701 	    CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF;  in nge_stats_update()
1703 	    CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF;  in nge_stats_update()
1705 	    CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF;  in nge_stats_update()
1707 	    CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF;  in nge_stats_update()
1709 	    CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF;  in nge_stats_update()
1711 	    CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF;  in nge_stats_update()
1713 	    CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF;  in nge_stats_update()
1715 	    CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF;  in nge_stats_update()
1717 	    CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF;  in nge_stats_update()
1774 		status = CSR_READ_4(sc, NGE_ISR);  in nge_poll()
1808 	status = CSR_READ_4(sc, NGE_ISR);  in nge_intr()
1824 		    CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT);  in nge_intr()
1844 		status = CSR_READ_4(sc, NGE_ISR);  in nge_intr()
1856 		    CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT);  in nge_intr()
2183 	reg = CSR_READ_4(sc, NGE_MIBCTL);  in nge_init_locked()
2425 	reg = CSR_READ_4(sc, NGE_CSR);  in nge_stop_mac()
2432 			if ((CSR_READ_4(sc, NGE_CSR) &  in nge_stop_mac()
2551 		reg = CSR_READ_4(sc, NGE_CLKRUN);  in nge_wol()