Lines Matching refs:CSR_READ_4
307 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
334 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
372 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
398 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
449 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
493 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
524 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
707 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
721 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
746 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); in alc_get_macaddr_813x()
748 CSR_READ_4(sc, ALC_WOL_CFG); in alc_get_macaddr_813x()
750 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | in alc_get_macaddr_813x()
754 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & in alc_get_macaddr_813x()
772 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
809 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
818 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
831 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
835 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
846 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
864 ea[0] = CSR_READ_4(sc, ALC_PAR0); in alc_get_macaddr_par()
865 ea[1] = CSR_READ_4(sc, ALC_PAR1); in alc_get_macaddr_par()
881 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_disable_l0s_l1()
1020 val = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_phy_reset_816x()
1052 val = CSR_READ_4(sc, ALC_LPI_CTL); in alc_phy_reset_816x()
1101 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_phy_down()
1156 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_aspm_813x()
1240 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_aspm_816x()
1278 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); in alc_init_pcie()
1284 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); in alc_init_pcie()
1286 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | in alc_init_pcie()
1290 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); in alc_init_pcie()
1322 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); in alc_init_pcie()
1325 val = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_init_pcie()
1357 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); in alc_config_msi()
1450 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) in alc_attach()
1477 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> in alc_attach()
1489 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, in alc_attach()
1490 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); in alc_attach()
2540 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); in alc_setwol_813x()
2546 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2554 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2561 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_813x()
2570 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); in alc_setwol_813x()
2577 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2593 master = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_setwol_816x()
2595 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_setwol_816x()
2602 mac = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_816x()
2613 mac = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_816x()
2625 reg = CSR_READ_4(sc, ALC_MISC); in alc_setwol_816x()
2633 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); in alc_setwol_816x()
3139 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_mac_config()
3187 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); in alc_stats_clear()
3193 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); in alc_stats_clear()
3224 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); in alc_stats_update()
3230 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); in alc_stats_update()
3328 status = CSR_READ_4(sc, ALC_INTR_STATUS); in alc_intr()
3349 status = CSR_READ_4(sc, ALC_INTR_STATUS); in alc_int_task()
3396 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { in alc_int_task()
3436 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); in alc_txeof()
3776 reg = CSR_READ_4(sc, ALC_MISC3); in alc_osc_reset()
3781 reg = CSR_READ_4(sc, ALC_MISC); in alc_osc_reset()
3792 reg = CSR_READ_4(sc, ALC_MISC2); in alc_osc_reset()
3822 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_reset()
3831 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_reset()
3838 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) in alc_reset()
3846 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) in alc_reset()
3853 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_reset()
3865 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_reset()
3875 reg = CSR_READ_4(sc, ALC_MISC3); in alc_reset()
3879 reg = CSR_READ_4(sc, ALC_MISC); in alc_reset()
3890 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | in alc_reset()
3960 CSR_READ_4(sc, ALC_WOL_CFG); in alc_init_locked()
4044 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_init_locked()
4169 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); in alc_init_locked()
4185 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); in alc_init_locked()
4319 reg = CSR_READ_4(sc, ALC_DMA_CFG); in alc_stop()
4369 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_stop_mac()
4375 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_stop_mac()
4400 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); in alc_start_queue()
4408 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); in alc_start_queue()
4420 reg = CSR_READ_4(sc, ALC_RXQ_CFG); in alc_stop_queue()
4433 reg = CSR_READ_4(sc, ALC_TXQ_CFG); in alc_stop_queue()
4440 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_stop_queue()
4560 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_rxvlan()
4592 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_rxfilter()