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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dxilinx_can.txt1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
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H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilin
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H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-…
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dxilinx-xadc.txt6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
16 communication. Xilinx provides a standard IP core that can be used to access the
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
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H A Dxlnx,zynqmp-ams.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-am
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dxlnx,zynq-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq
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H A Dxlnx,zynq-pinctrl.txt1 Binding for Xilinx Zynq Pinctrl
4 - compatible: "xlnx,zynq-pinctrl"
5 - syscon: phandle to SLCR
6 - reg: Offset and length of pinctrl space in SLCR
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Zynq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
16 parameters, such as pull-up, slew rate, etc.
18 Each configuration node can consist of multiple nodes describing the pinmux and
19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
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/freebsd/share/man/man4/
H A Dcgem.48 .\" 1. Redistributions of source code must retain the above copyright
35 .Bd -ragged -offset indent
45 the Xilinx Zynq-7000, the Xilinx Zynq UltraScale+, and the SiFive
51 .Bl -tag -width ".Cm 10baseT/UTP"
54 The user can manually override
64 option can also be used to select either
65 .Cm full-duplex
67 .Cm half-duplex
74 option can also be used to select either
75 .Cm full-duplex
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/freebsd/share/man/man4/man4.arm/
H A Ddevcfg.48 .\" 1. Redistributions of source code must retain the above copyright
30 .Nd Zynq PL device config interface
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
45 shifters and release the top-level PL reset signals.
47 The PL (FPGA) can be configured by writing the bitstream to the character
49 .Bd -literal -offset indent
58 tool can do the conversion:
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
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/freebsd/sys/arm/xilinx/
H A Dzy7_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
30 * A GPIO driver for Xilinx Zynq-7000.
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
71 /* Zynq 7000 */
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H A Dzy7_slcr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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H A Dzy7_qspi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
31 * This is a driver for the Quad-SPI Flash Controller in the Xilinx
32 * Zynq-7000 SoC.
63 {"xlnx,zy7_qspi", 1},
64 {"xlnx,zynq-qspi-1.0", 1},
98 #define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
99 #define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
101 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
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H A Dzy7_spi.c1 /*-
8 * 1. Redistributions of source code must retain the above copyright
53 {"xlnx,zy7_spi", 1},
54 {"xlnx,zynq-spi-1.0", 1},
55 {"cdns,spi-r1p6", 1},
85 #define SPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
86 #define SPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
88 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
89 #define SPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
90 #define SPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdr
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H A Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
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/freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmwar
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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
82 ---
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
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/freebsd/sys/dev/cadence/
H A Dif_cgem.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com>
10 * 1. Redistributions of source code must retain the above copyright
31 * interface such as the one used in Xilinx Zynq-7000 SoC.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
102 #define HWQUIRK_NEEDNULLQS 1
106 { "cdns,zynq-gem", HWQUIRK_RXHANGWAR }, /* Deprecated */
107 { "cdns,zynqmp-gem", HWQUIRK_NEEDNULLQS }, /* Deprecated */
108 { "xlnx,zynq-gem", HWQUIRK_RXHANGWAR },
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/freebsd/sys/dev/iicbus/controller/cadence/
H A Dcdnc_i2c.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2019-2020 Thomas Skibo <thomasskibo@yahoo.com>
9 * 1. Redistributions of source code must retain the above copyright
28 /* Cadence / Zynq i2c driver.
30 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
31 * (v1.12.2) July 1, 2018. Xilinx doc UG585. I2C Controller is documented
69 #define HWTYPE_CDNS_R1P10 1
75 {"cdns,i2c-r1p10", HWTYPE_CDNS_R1P10},
77 {"cdns,i2c-r1p14", HWTYPE_CDNS_R1P14},
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
9 * This program is free software; you can redistribute it and/or
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-binding
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/freebsd/sys/dev/sdhci/
H A Dsdhci_fdt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
11 * 1. Redistributions of source code must retain the above copyright
71 #define SDHCI_FDT_ARMADA38X 1
80 #define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7)
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
116 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X },
117 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM },
118 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 },
120 { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 },
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/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2024-09-20 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
13 # This file can be distributed under either the GNU General Public License
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
49 7a19 PCI-to-PCI Bridge
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