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/linux/Documentation/devicetree/bindings/reset/
H A Dthead,th1520-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/thead,th1520-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD TH1520 SoC Reset Controller
10 The T-HEAD TH1520 reset controller is a hardware block that asserts/deasserts
14 - Michal Wilczynski <m.wilczynski@samsung.com>
19 - thead,th1520-reset
24 "#reset-cells":
28 - compatible
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/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD TH1520 GPU Power Sequencer Driver
8 * This driver implements the power sequence for the Imagination BXM-4-64
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
11 * device node (clocks and core reset).
14 * GPU driver requests the "gpu-power" sequence target.
23 #include <linux/reset.h>
26 #include <dt-bindings/power/thead,th1520-power.h>
45 if (!ctx->clks || !ctx->gpu_reset) in pwrseq_thead_gpu_enable()
46 return -ENODEV; in pwrseq_thead_gpu_enable()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 during power-up.
26 former two share the power-up sequence which is executed by the PMU,
31 tristate "T-HEAD TH1520 GPU power sequencing driver"
34 Say Y here to enable the power sequencing driver for the TH1520 SoC
35 GPU. This driver handles the complex clock and reset sequence
/linux/Documentation/devicetree/bindings/firmware/
H A Dthead,th1520-aon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD TH1520 AON (Always-On) Firmware
10 The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing
11 low-power states, system wakeup events, and power management tasks. It is
15 At the heart of the AON subsystem is the E902, a low-power core that executes
19 enables message-based interactions with the AON firmware.
22 - Michal Wilczynski <m.wilczynski@samsung.com>
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dthead,th1520-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
15 The TH1520 has 3 groups of pads each controlled from different memory ranges.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
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/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 tristate "ASPEED Reset Driver"
30 This enables the reset controller driver for AST2700.
33 bool "AR71xx Reset Driver" if COMPILE_TEST
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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/linux/arch/riscv/boot/dts/thead/
H A Dth1520-beaglev-ahead.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "th1520.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
15 compatible = "beagle,beaglev-ahead", "thead,th1520";
35 stdout-path = "serial0:115200n8";
44 pinctrl-names = "default";
45 pinctrl-0 = <&led_pins>;
46 compatible = "gpio-leds";
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - enum:
18 - rockchip,rk3528-dwcmshc
19 - rockchip,rk3562-dwcmshc
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/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
136 [TH1520_MUX_RST] = "reset",
340 .name = "th1520-group1",
346 .name = "th1520-group2",
352 .name = "th1520-group3",
361 return thp->desc.npins; in th1520_pinctrl_get_groups_count()
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/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux/drivers/mmc/host/
H A Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
22 #include <linux/reset.h>
25 #include "sdhci-pltfm.h"
42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
119 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
140 /* PHY reset pad settings */
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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