xref: /linux/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
1169162caSShawn Lin# SPDX-License-Identifier: GPL-2.0-only
2169162caSShawn Lin%YAML 1.2
3169162caSShawn Lin---
4169162caSShawn Lin$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5169162caSShawn Lin$schema: http://devicetree.org/meta-schemas/core.yaml#
6169162caSShawn Lin
784e85359SKrzysztof Kozlowskititle: Synopsys Designware Mobile Storage Host Controller
8169162caSShawn Lin
9169162caSShawn Linmaintainers:
10169162caSShawn Lin  - Ulf Hansson <ulf.hansson@linaro.org>
11169162caSShawn Lin  - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
12169162caSShawn Lin
13169162caSShawn Linproperties:
14169162caSShawn Lin  compatible:
15*7e856617SDetlev Casanova    oneOf:
16*7e856617SDetlev Casanova      - items:
17*7e856617SDetlev Casanova          - const: rockchip,rk3576-dwcmshc
18*7e856617SDetlev Casanova          - const: rockchip,rk3588-dwcmshc
19*7e856617SDetlev Casanova      - enum:
20dd12261eSShawn Lin          - rockchip,rk3568-dwcmshc
21bbbd8872SSebastian Reichel          - rockchip,rk3588-dwcmshc
22169162caSShawn Lin          - snps,dwcmshc-sdhci
23849e8181SJisheng Zhang          - sophgo,cv1800b-dwcmshc
24849e8181SJisheng Zhang          - sophgo,sg2002-dwcmshc
25fc7b9168SChen Wang          - sophgo,sg2042-dwcmshc
26edee9553SDrew Fustini          - thead,th1520-dwcmshc
27169162caSShawn Lin
28169162caSShawn Lin  reg:
2967006e30SRob Herring    maxItems: 1
30169162caSShawn Lin
31169162caSShawn Lin  interrupts:
32169162caSShawn Lin    maxItems: 1
33169162caSShawn Lin
34169162caSShawn Lin  clocks:
35169162caSShawn Lin    minItems: 1
36fc7b9168SChen Wang    maxItems: 5
37169162caSShawn Lin
38169162caSShawn Lin  clock-names:
39169162caSShawn Lin    minItems: 1
40fc7b9168SChen Wang    maxItems: 5
41dd12261eSShawn Lin
42*7e856617SDetlev Casanova  power-domains:
43*7e856617SDetlev Casanova    maxItems: 1
44*7e856617SDetlev Casanova
455cb7d237SSebastian Reichel  resets:
465cb7d237SSebastian Reichel    maxItems: 5
475cb7d237SSebastian Reichel
485cb7d237SSebastian Reichel  reset-names:
495cb7d237SSebastian Reichel    items:
505cb7d237SSebastian Reichel      - const: core
515cb7d237SSebastian Reichel      - const: bus
525cb7d237SSebastian Reichel      - const: axi
535cb7d237SSebastian Reichel      - const: block
545cb7d237SSebastian Reichel      - const: timer
555cb7d237SSebastian Reichel
56dd12261eSShawn Lin  rockchip,txclk-tapnum:
57dd12261eSShawn Lin    description: Specify the number of delay for tx sampling.
58dd12261eSShawn Lin    $ref: /schemas/types.yaml#/definitions/uint8
59dd12261eSShawn Lin
60169162caSShawn Linrequired:
61169162caSShawn Lin  - compatible
62169162caSShawn Lin  - reg
63169162caSShawn Lin  - interrupts
64169162caSShawn Lin  - clocks
65169162caSShawn Lin  - clock-names
66169162caSShawn Lin
67fc7b9168SChen WangallOf:
68fc7b9168SChen Wang  - $ref: mmc-controller.yaml#
69fc7b9168SChen Wang
70fc7b9168SChen Wang  - if:
71fc7b9168SChen Wang      properties:
72fc7b9168SChen Wang        compatible:
73fc7b9168SChen Wang          contains:
74fc7b9168SChen Wang            const: sophgo,sg2042-dwcmshc
75fc7b9168SChen Wang
76fc7b9168SChen Wang    then:
77fc7b9168SChen Wang      properties:
78fc7b9168SChen Wang        clocks:
79fc7b9168SChen Wang          items:
80fc7b9168SChen Wang            - description: core clock
81fc7b9168SChen Wang            - description: bus clock
82fc7b9168SChen Wang            - description: timer clock
83fc7b9168SChen Wang        clock-names:
84fc7b9168SChen Wang          items:
85fc7b9168SChen Wang            - const: core
86fc7b9168SChen Wang            - const: bus
87fc7b9168SChen Wang            - const: timer
88fc7b9168SChen Wang    else:
89fc7b9168SChen Wang      properties:
90fc7b9168SChen Wang        clocks:
91fc7b9168SChen Wang          minItems: 1
92fc7b9168SChen Wang          items:
93fc7b9168SChen Wang            - description: core clock
94fc7b9168SChen Wang            - description: bus clock for optional
95fc7b9168SChen Wang            - description: axi clock for rockchip specified
96fc7b9168SChen Wang            - description: block clock for rockchip specified
97fc7b9168SChen Wang            - description: timer clock for rockchip specified
98fc7b9168SChen Wang        clock-names:
99fc7b9168SChen Wang          minItems: 1
100fc7b9168SChen Wang          items:
101fc7b9168SChen Wang            - const: core
102fc7b9168SChen Wang            - const: bus
103fc7b9168SChen Wang            - const: axi
104fc7b9168SChen Wang            - const: block
105fc7b9168SChen Wang            - const: timer
106fc7b9168SChen Wang
107*7e856617SDetlev Casanova  - if:
108*7e856617SDetlev Casanova      properties:
109*7e856617SDetlev Casanova        compatible:
110*7e856617SDetlev Casanova          contains:
111*7e856617SDetlev Casanova            const: rockchip,rk3576-dwcmshc
112*7e856617SDetlev Casanova
113*7e856617SDetlev Casanova    then:
114*7e856617SDetlev Casanova      required:
115*7e856617SDetlev Casanova        - power-domains
116*7e856617SDetlev Casanova
117*7e856617SDetlev Casanova    else:
118*7e856617SDetlev Casanova      properties:
119*7e856617SDetlev Casanova        power-domains: false
120*7e856617SDetlev Casanova
121169162caSShawn LinunevaluatedProperties: false
122169162caSShawn Lin
123169162caSShawn Linexamples:
124169162caSShawn Lin  - |
125dd12261eSShawn Lin    mmc@fe310000 {
126dd12261eSShawn Lin      compatible = "rockchip,rk3568-dwcmshc";
127dd12261eSShawn Lin      reg = <0xfe310000 0x10000>;
128dd12261eSShawn Lin      interrupts = <0 25 0x4>;
129dd12261eSShawn Lin      clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
130dd12261eSShawn Lin      clock-names = "core", "bus", "axi", "block", "timer";
131dd12261eSShawn Lin      bus-width = <8>;
132dd12261eSShawn Lin      #address-cells = <1>;
133dd12261eSShawn Lin      #size-cells = <0>;
134dd12261eSShawn Lin    };
135dd12261eSShawn Lin  - |
136169162caSShawn Lin    mmc@aa0000 {
137169162caSShawn Lin      compatible = "snps,dwcmshc-sdhci";
138169162caSShawn Lin      reg = <0xaa000 0x1000>;
139169162caSShawn Lin      interrupts = <0 25 0x4>;
140169162caSShawn Lin      clocks = <&cru 17>, <&cru 18>;
141169162caSShawn Lin      clock-names = "core", "bus";
142169162caSShawn Lin      bus-width = <8>;
143169162caSShawn Lin      #address-cells = <1>;
144169162caSShawn Lin      #size-cells = <0>;
145169162caSShawn Lin    };
146169162caSShawn Lin
147169162caSShawn Lin...
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