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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-stm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The STM is a trace source that is integrated into a CoreSight system, designed
24 primarily for high-bandwidth trace of instrumentation embedded into software.
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H A Dcoresight.txt11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
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H A Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1 //===- SILoadStoreOptimizer.cpp -------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 // adjusting the base. It tries to use a base from the nearby instructions that
45 // - This is currently missing stores of constants because loading
49 // - Live interval recomputing seems inefficient. This currently only matches
53 // - With a list of instructions to process, we can also merge more. If a
54 // cluster of loads have offsets that are too large to fit in the 8-bit
55 // offsets, but are close enough to fit in the 8 bits, we can add to the base
58 //===----------------------------------------------------------------------===//
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
74 #define DEBUG_TYPE "arm-ldst-opt"
77 STATISTIC(NumSTMGened , "Number of stm instructions generated");
84 STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
94 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
101 /// Post- register allocation pass the combine load / store instructions to
102 /// form ldm / stm instructions.
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H A DARMInstrThumb.td1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
22 unsigned Imm = N->getZExtValue();
23 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
27 uint64_t Imm = N->getZExtValue();
35 return (uint32_t)-N->getZExtValue() < 8;
40 unsigned Value = -(unsigned)N->getZExtValue();
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H A DARMISelLowering.h1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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H A DARMAsmPrinter.cpp1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //===----------------------------------------------------------------------===//
51 #define DEBUG_TYPE "asm-printer"
56 MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {} in ARMAsmPrinter()
64 OutStreamer->emitDataRegion(MCDR_DataRegionEnd); in emitFunctionBodyEnd()
68 if (AFI->isThumbFunction()) { in emitFunctionEntryLabel()
69 OutStreamer->emitAssemblerFlag(MCAF_Code16); in emitFunctionEntryLabel()
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H A DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
257 // VDUPLANE can produce a quad-register result from a double-register source,
313 // reinterprets the _register_ format - and in big-endian, the memory and
318 // whereas 'bitconvert' will map it to the high byte in big-endian mode,
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H A DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
72 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
74 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
78 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
80 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
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/freebsd/contrib/opencsd/decoder/source/stm/
H A Dtrc_pkt_decode_stm.cpp3 * \brief OpenCSD : STM packet decoder - output generic SW trace packets.
35 #include "opencsd/stm/trc_pkt_decode_stm.h"
77 if(m_curr_packet_in->getPktType() == STM_PKT_ASYNC) in processPacket()
119 // static config - copy of CSID for easy reference in onProtocolConfig()
120 m_CSID = m_config->getTraceID(); in onProtocolConfig()
127 m_num_pkt_correlation = 1; // fixed at single packet payload correlation - add feature later in initDecoder()
130 // base decoder state - STM requires no memory and instruction decode. in initDecoder()
167 switch (m_curr_packet_in->getPktType()) in decodePacket()
177 case STM_PKT_VERSION: /**< Version packet - not relevant to generic (versionless) o/p */ in decodePacket()
185 if(m_curr_packet_in->isTSPkt()) in decodePacket()
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/freebsd/contrib/opencsd/decoder/include/
H A Dopencsd.h3 * \brief OpenCSD: Open CoreSight Trace Decoder -Master include file for C++ library
53 /* protocol base classes and generic elements */
65 #include "opencsd/stm/stm_decoder.h"
/freebsd/sys/arm/arm/
H A Ddisassem.c3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
71 * 2 - print Operand 2 of a data processing instruction
72 * d - destination register (bits 12-15)
73 * n - n register (bits 16-19)
74 * s - s register (bits 8-11)
75 * o - indirect register rn (bits 16-19) (used by swap)
76 * m - m register (bits 0-3)
77 * a - address operand of ldr/str instruction
78 * l - register list for ldm/stm instruction
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/freebsd/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-s390x.pl21 # ~6.6/2.3 cpb on z10/z196+, >2x improvement over compiler-generated
23 # then base 2^64 and base 2^32 implementations are compared.
25 # On side note, z13 enables vector base 2^26 implementation...
30 # Add vx code path (base 2^26).
38 # Add vector base 2^26 implementation. It's problematic to accurately
40 # it's sub-cycle, i.e. less than 1 cycle per processed byte, and it's
82 lghi ("%r1",-1);
93 lrvg ("%r2","0($inp)"); # load little-endian key
117 &{$z? \&stmg:\&stm} ("%r2","%r3","0(%r4)");
121 SIZE ("poly1305_init",".-poly1305_init");
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cell
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/freebsd/contrib/opencsd/decoder/include/common/
H A Dtrc_pkt_decode_base.h3 * \brief OpenCSD : Trace Packet decoder base class.
53 Packet decoders can be:-
54 - PE decoders - converting ETM or PTM packets into instruction and data trace elements
55 - SW stimulus decoder - converting STM or ITM packets into software generated trace elements.
56 - Bus decoders - converting HTM packets into bus transaction elements.
162 return m_trace_elem_out.first()->TraceElemIn(m_index_curr_pkt,getCoreSightTraceID(), elem); in outputTraceElement()
167 return m_trace_elem_out.first()->TraceElemIn(idx, getCoreSightTraceID(), elem); in outputTraceElementIdx()
173 return m_instr_decode.first()->DecodeInstruction(instr_info); in instrDecode()
180 …return m_mem_access.first()->ReadTargetMemory(address,getCoreSightTraceID(),mem_space, num_bytes,p… in accessMemory()
188 m_mem_access.first()->InvalidateMemAccCache(getCoreSightTraceID()); in invalidateMemAccCache()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCodeGenPGO.cpp1 //===--- CodeGenPGO.cpp - PGO Instrumentation for LLVM CodeGen --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Instrumentation-based profile-guided optimization
11 //===----------------------------------------------------------------------===//
31 EnableValueProfiling("enable-value-profiling",
43 PGOReader ? PGOReader->getVersion() : llvm::IndexedInstrProf::Version); in setFuncName()
51 setFuncName(Fn->getName(), Fn->getLinkage()); in setFuncName()
72 /// profiles -- i.e., don't do it.
151 if (PGOReader->getVersion() <= 4) in getPGOHashVersion()
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/freebsd/contrib/opencsd/decoder/include/opencsd/
H A Docsd_if_types.h41 /** VS2010 does not support inttypes - remove when VS2010 support is dropped */
64 typedef uint64_t ocsd_trc_index_t; /**< Trace source index type - 64 bit size */
67 typedef uint32_t ocsd_trc_index_t; /**< Trace source index type - 32 bit size */
72 #define OCSD_BAD_TRC_INDEX ((ocsd_trc_index_t)-1)
74 #define OCSD_BAD_CS_SRC_ID ((uint8_t)-1)
99 OCSD_ERR_ATTACH_TOO_MANY, /**< Cannot attach - attach device limit reached. */
100 OCSD_ERR_ATTACH_INVALID_PARAM, /**< Cannot attach - invalid parameter. */
101 OCSD_ERR_ATTACH_COMP_NOT_FOUND,/**< Cannot detach - component not found. */
103 OCSD_ERR_RDR_FILE_NOT_FOUND, /**< source reader - file not found. */
104 OCSD_ERR_RDR_INVALID_INIT, /**< source reader - invalid initialisation parameter. */
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm891
571 stm: stm@802000 { global() label
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H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm899
1618 stm: stm@6002000 { global() label
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-binding
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H A Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm899
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/freebsd/sys/dev/acpica/
H A Dacpi_resource.c1 /*-
81 switch (res->Type) { in acpi_lookup_irq_handler()
83 irqnum = res->Data.Irq.InterruptCount; in acpi_lookup_irq_handler()
85 if (res->Data.Irq.Interrupts[i] == req->irq) { in acpi_lookup_irq_handler()
91 trig = res->Data.Irq.Triggering; in acpi_lookup_irq_handler()
92 pol = res->Data.Irq.Polarity; in acpi_lookup_irq_handler()
95 irqnum = res->Data.ExtendedIrq.InterruptCount; in acpi_lookup_irq_handler()
97 if (res->Data.ExtendedIrq.Interrupts[i] == req->irq) { in acpi_lookup_irq_handler()
103 trig = res->Data.ExtendedIrq.Triggering; in acpi_lookup_irq_handler()
104 pol = res->Data.ExtendedIrq.Polarity; in acpi_lookup_irq_handler()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
27 // The ABI-defined register save slots, relative to the CFA (i.e.
66 STI.getTargetLowering()->getTargetMachine().getPointerSize(0); in create()
77 uint32_t D12Count = 0; // 12-bit displacement only.
83 // TODO: Move to base class.
100 // Examine uses for each object and record short (12-bit) and "pair" in orderFrameObjects()
113 if (TII->hasDisplacementPairInsn(MI.getOpcode())) in orderFrameObjects()
158 // we're using a frame pointer. Similarly, 64-bit XPLINK requires 96 bytes in hasReservedCallFrame()
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