Lines Matching +full:stm +full:- +full:base
1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
79 INTRET_GLUE, // Interrupt return with an LR-offset and a flag operand.
104 SRL_GLUE, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
105 SRA_GLUE, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
106 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
135 WLS, // Low-overhead loops, While Loop Start branch. See t2WhileLoopStart
138 LE, // Low-overhead loops, Loop End
183 // (These are used for 8- and 16-bit element types only.)
184 VGETLANEu, // zero-extend vector extract element
185 VGETLANEs, // sign-extend vector extract element
194 // Move H <-> R, clearing top 16 bits
204 VREV64, // reverse elements within 64-bit doublewords
205 VREV32, // reverse elements within 32-bit words
206 VREV16, // reverse elements within 16-bit halfwords
210 VTBL1, // 1-register shuffle with mask
211 VTBL2, // 2-register shuffle with mask
219 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top
221 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes
233 VADDVs, // sign- or zero-extend the elements of a vector to i32,
237 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
238 VADDLVu, // the low and high 32-bit halves of the sum
245 VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
250 VMLALVu, // high 32-bit halves of the sum
266 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
267 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
268 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
269 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
270 SMLALTT, // 64-bit signed accumulate multiply top, top 16
291 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
292 // operands need to be legalized. Define an ARM-specific version of
296 // Bit-field insert
307 // Pseudo-instruction representing a memory copy using ldm/stm
311 // Pseudo-instruction representing a memory copy using a tail predicated
314 // Pseudo-instruction representing a memset using a tail predicated
323 // Vector load N-element structure to all lanes:
329 // NEON loads with post-increment base updates:
345 // NEON stores with post-increment base updates:
378 // Bits of floating-point status. These are NZCV flags, QC bit and cumulative
394 //===--------------------------------------------------------------------===//
395 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
407 /// ReplaceNodeResults - Replace the results of node with an illegal result
421 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
449 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
474 /// isLegalAddressingMode - Return true if the addressing mode represented
486 /// isLegalICmpImmediate - Return true if the specified immediate is legal
492 /// isLegalAddImmediate - Return true if the specified immediate is legal
498 /// getPreIndexedAddressParts - returns true by value, base pointer and
500 /// can be legally represented as pre-indexed load / store address.
501 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
505 /// getPostIndexedAddressParts - returns true by value, base pointer and
507 /// combined with a load / store to form a post-indexed load / store.
508 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
536 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
577 /// getRegClassFor - Return the register class that should be used for the
585 /// createFastISel - This method returns a target specific FastISel object,
600 /// isFPImmLegal - Returns true if the target can instruction select the
774 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
900 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in supportSplitCSR()
901 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); in supportSplitCSR()
938 /// HandleByVal - Target-specific cleanup for ByVal support.
941 /// IsEligibleForTailCallOptimization - Check whether the call is eligible