Lines Matching +full:stm +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h>
14 interrupt-parent = <&intc>;
16 qcom,msm-id = <292 0x0>;
18 #address-cells = <2>;
19 #size-cells = <2>;
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
36 no-map;
41 no-map;
44 smem_mem: smem-mem@86000000 {
46 no-map;
51 no-map;
55 compatible = "qcom,rmtfs-mem";
57 no-map;
59 qcom,client-id = <1>;
65 no-map;
70 no-map;
75 no-map;
80 no-map;
85 no-map;
90 no-map;
95 no-map;
100 no-map;
105 no-map;
110 no-map;
113 mdata_mem: mpss-metadata {
114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
116 no-map;
121 xo: xo-board {
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <19200000>;
125 clock-output-names = "xo_board";
128 sleep_clk: sleep-clk {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <32764>;
136 #address-cells = <2>;
137 #size-cells = <0>;
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146 next-level-cache = <&L2_0>;
147 L2_0: l2-cache {
149 cache-level = <2>;
150 cache-unified;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161 next-level-cache = <&L2_0>;
168 enable-method = "psci";
169 capacity-dmips-mhz = <1024>;
170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L2_0>;
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181 next-level-cache = <&L2_0>;
188 enable-method = "psci";
189 capacity-dmips-mhz = <1536>;
190 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191 next-level-cache = <&L2_1>;
192 L2_1: l2-cache {
194 cache-level = <2>;
195 cache-unified;
203 enable-method = "psci";
204 capacity-dmips-mhz = <1536>;
205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206 next-level-cache = <&L2_1>;
213 enable-method = "psci";
214 capacity-dmips-mhz = <1536>;
215 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216 next-level-cache = <&L2_1>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1536>;
225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226 next-level-cache = <&L2_1>;
229 cpu-map {
267 idle-states {
268 entry-method = "psci";
270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271 compatible = "arm,idle-state";
272 idle-state-name = "little-retention";
274 arm,psci-suspend-param = <0x00000002>;
275 entry-latency-us = <81>;
276 exit-latency-us = <86>;
277 min-residency-us = <504>;
280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281 compatible = "arm,idle-state";
282 idle-state-name = "little-power-collapse";
284 arm,psci-suspend-param = <0x40000003>;
285 entry-latency-us = <814>;
286 exit-latency-us = <4562>;
287 min-residency-us = <9183>;
288 local-timer-stop;
291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "big-retention";
295 arm,psci-suspend-param = <0x00000002>;
296 entry-latency-us = <79>;
297 exit-latency-us = <82>;
298 min-residency-us = <1302>;
301 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "big-power-collapse";
305 arm,psci-suspend-param = <0x40000003>;
306 entry-latency-us = <724>;
307 exit-latency-us = <2027>;
308 min-residency-us = <9419>;
309 local-timer-stop;
316 compatible = "qcom,scm-msm8998", "qcom,scm";
320 dsi_opp_table: opp-table-dsi {
321 compatible = "operating-points-v2";
323 opp-131250000 {
324 opp-hz = /bits/ 64 <131250000>;
325 required-opps = <&rpmpd_opp_low_svs>;
328 opp-210000000 {
329 opp-hz = /bits/ 64 <210000000>;
330 required-opps = <&rpmpd_opp_svs>;
333 opp-312500000 {
334 opp-hz = /bits/ 64 <312500000>;
335 required-opps = <&rpmpd_opp_nom>;
340 compatible = "arm,psci-1.0";
345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
347 glink-edge {
348 compatible = "qcom,glink-rpm";
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-msm8998";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
361 clock-names = "xo";
362 #clock-cells = <1>;
365 rpmpd: power-controller {
366 compatible = "qcom,msm8998-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
374 opp-level = <RPM_SMD_LEVEL_RETENTION>;
378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
390 opp-level = <RPM_SMD_LEVEL_SVS>;
394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_NOM>;
402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
406 opp-level = <RPM_SMD_LEVEL_TURBO>;
410 opp-level = <RPM_SMD_LEVEL_BINNING>;
420 memory-region = <&smem_mem>;
424 smp2p-lpass {
432 qcom,local-pid = <0>;
433 qcom,remote-pid = <2>;
435 adsp_smp2p_out: master-kernel {
436 qcom,entry-name = "master-kernel";
437 #qcom,smem-state-cells = <1>;
440 adsp_smp2p_in: slave-kernel {
441 qcom,entry-name = "slave-kernel";
443 interrupt-controller;
444 #interrupt-cells = <2>;
448 smp2p-mpss {
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <1>;
456 modem_smp2p_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 modem_smp2p_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
468 smp2p-slpi {
473 qcom,local-pid = <0>;
474 qcom,remote-pid = <3>;
476 slpi_smp2p_out: master-kernel {
477 qcom,entry-name = "master-kernel";
478 #qcom,smem-state-cells = <1>;
481 slpi_smp2p_in: slave-kernel {
482 qcom,entry-name = "slave-kernel";
483 interrupt-controller;
484 #interrupt-cells = <2>;
488 thermal-zones {
489 cpu0-thermal {
490 polling-delay-passive = <250>;
491 polling-delay = <1000>;
493 thermal-sensors = <&tsens0 1>;
496 cpu0_alert0: trip-point0 {
502 cpu0_crit: cpu-crit {
510 cpu1-thermal {
511 polling-delay-passive = <250>;
512 polling-delay = <1000>;
514 thermal-sensors = <&tsens0 2>;
517 cpu1_alert0: trip-point0 {
523 cpu1_crit: cpu-crit {
531 cpu2-thermal {
532 polling-delay-passive = <250>;
533 polling-delay = <1000>;
535 thermal-sensors = <&tsens0 3>;
538 cpu2_alert0: trip-point0 {
544 cpu2_crit: cpu-crit {
552 cpu3-thermal {
553 polling-delay-passive = <250>;
554 polling-delay = <1000>;
556 thermal-sensors = <&tsens0 4>;
559 cpu3_alert0: trip-point0 {
565 cpu3_crit: cpu-crit {
573 cpu4-thermal {
574 polling-delay-passive = <250>;
575 polling-delay = <1000>;
577 thermal-sensors = <&tsens0 7>;
580 cpu4_alert0: trip-point0 {
586 cpu4_crit: cpu-crit {
594 cpu5-thermal {
595 polling-delay-passive = <250>;
596 polling-delay = <1000>;
598 thermal-sensors = <&tsens0 8>;
601 cpu5_alert0: trip-point0 {
607 cpu5_crit: cpu-crit {
615 cpu6-thermal {
616 polling-delay-passive = <250>;
617 polling-delay = <1000>;
619 thermal-sensors = <&tsens0 9>;
622 cpu6_alert0: trip-point0 {
628 cpu6_crit: cpu-crit {
636 cpu7-thermal {
637 polling-delay-passive = <250>;
638 polling-delay = <1000>;
640 thermal-sensors = <&tsens0 10>;
643 cpu7_alert0: trip-point0 {
649 cpu7_crit: cpu-crit {
657 gpu-bottom-thermal {
658 polling-delay-passive = <250>;
659 polling-delay = <1000>;
661 thermal-sensors = <&tsens0 12>;
664 gpu1_alert0: trip-point0 {
672 gpu-top-thermal {
673 polling-delay-passive = <250>;
674 polling-delay = <1000>;
676 thermal-sensors = <&tsens0 13>;
679 gpu2_alert0: trip-point0 {
687 clust0-mhm-thermal {
688 polling-delay-passive = <250>;
689 polling-delay = <1000>;
691 thermal-sensors = <&tsens0 5>;
694 cluster0_mhm_alert0: trip-point0 {
702 clust1-mhm-thermal {
703 polling-delay-passive = <250>;
704 polling-delay = <1000>;
706 thermal-sensors = <&tsens0 6>;
709 cluster1_mhm_alert0: trip-point0 {
717 cluster1-l2-thermal {
718 polling-delay-passive = <250>;
719 polling-delay = <1000>;
721 thermal-sensors = <&tsens0 11>;
724 cluster1_l2_alert0: trip-point0 {
732 modem-thermal {
733 polling-delay-passive = <250>;
734 polling-delay = <1000>;
736 thermal-sensors = <&tsens1 1>;
739 modem_alert0: trip-point0 {
747 mem-thermal {
748 polling-delay-passive = <250>;
749 polling-delay = <1000>;
751 thermal-sensors = <&tsens1 2>;
754 mem_alert0: trip-point0 {
762 wlan-thermal {
763 polling-delay-passive = <250>;
764 polling-delay = <1000>;
766 thermal-sensors = <&tsens1 3>;
769 wlan_alert0: trip-point0 {
777 q6-dsp-thermal {
778 polling-delay-passive = <250>;
779 polling-delay = <1000>;
781 thermal-sensors = <&tsens1 4>;
784 q6_dsp_alert0: trip-point0 {
792 camera-thermal {
793 polling-delay-passive = <250>;
794 polling-delay = <1000>;
796 thermal-sensors = <&tsens1 5>;
799 camera_alert0: trip-point0 {
807 multimedia-thermal {
808 polling-delay-passive = <250>;
809 polling-delay = <1000>;
811 thermal-sensors = <&tsens1 6>;
814 multimedia_alert0: trip-point0 {
824 compatible = "arm,armv8-timer";
832 #address-cells = <1>;
833 #size-cells = <1>;
835 compatible = "simple-bus";
837 gcc: clock-controller@100000 {
838 compatible = "qcom,gcc-msm8998";
839 #clock-cells = <1>;
840 #reset-cells = <1>;
841 #power-domain-cells = <1>;
844 clock-names = "xo", "sleep_clk";
849 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
851 * enabled but unused during boot-up), the device will most likely decide
854 * as protected. The board dts (or a user-supplied dts) can override the
858 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
864 compatible = "qcom,rpm-msg-ram";
869 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
871 #address-cells = <1>;
872 #size-cells = <1>;
874 qusb2_hstx_trim: hstx-trim@23a {
881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
887 interrupt-names = "uplow", "critical";
888 #thermal-sensor-cells = <1>;
892 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
898 interrupt-names = "uplow", "critical";
899 #thermal-sensor-cells = <1>;
903 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
905 #iommu-cells = <1>;
907 #global-interrupts = <0>;
918 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
920 #iommu-cells = <1>;
922 #global-interrupts = <0>;
937 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
942 reg-names = "parf", "dbi", "elbi", "config";
944 linux,pci-domain = <0>;
945 bus-range = <0x00 0xff>;
946 #address-cells = <3>;
947 #size-cells = <2>;
948 num-lanes = <1>;
950 phy-names = "pciephy";
956 #interrupt-cells = <1>;
958 interrupt-names = "msi";
959 interrupt-map-mask = <0 0 0 0x7>;
960 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
970 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
972 power-domains = <&gcc PCIE_0_GDSC>;
973 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
974 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
978 compatible = "qcom,msm8998-qmp-pcie-phy";
986 clock-names = "aux",
991 clock-output-names = "pcie_0_pipe_clk_src";
992 #clock-cells = <0>;
994 #phy-cells = <0>;
997 reset-names = "phy", "common";
999 vdda-phy-supply = <&vreg_l1a_0p875>;
1000 vdda-pll-supply = <&vreg_l2a_1p2>;
1004 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1008 phy-names = "ufsphy";
1009 lanes-per-direction = <2>;
1010 power-domains = <&gcc UFS_GDSC>;
1012 #reset-cells = <1>;
1014 clock-names =
1032 freq-table-hz =
1043 reset-names = "rst";
1047 compatible = "qcom,msm8998-qmp-ufs-phy";
1050 clock-names =
1057 reset-names = "ufsphy";
1060 #phy-cells = <0>;
1065 compatible = "qcom,tcsr-mutex";
1067 #hwlock-cells = <1>;
1071 compatible = "qcom,msm8998-tcsr", "syscon";
1076 compatible = "qcom,msm8998-pinctrl";
1079 gpio-ranges = <&tlmm 0 0 150>;
1080 gpio-controller;
1081 #gpio-cells = <2>;
1082 interrupt-controller;
1083 #interrupt-cells = <2>;
1085 sdc2_on: sdc2-on-state {
1086 clk-pins {
1088 drive-strength = <16>;
1089 bias-disable;
1092 cmd-pins {
1094 drive-strength = <10>;
1095 bias-pull-up;
1098 data-pins {
1100 drive-strength = <10>;
1101 bias-pull-up;
1105 sdc2_off: sdc2-off-state {
1106 clk-pins {
1108 drive-strength = <2>;
1109 bias-disable;
1112 cmd-pins {
1114 drive-strength = <2>;
1115 bias-pull-up;
1118 data-pins {
1120 drive-strength = <2>;
1121 bias-pull-up;
1125 sdc2_cd: sdc2-cd-state {
1128 bias-pull-up;
1129 drive-strength = <2>;
1132 blsp1_uart3_on: blsp1-uart3-on-state {
1133 tx-pins {
1136 drive-strength = <2>;
1137 bias-disable;
1140 rx-pins {
1143 drive-strength = <2>;
1144 bias-disable;
1147 cts-pins {
1150 drive-strength = <2>;
1151 bias-disable;
1154 rfr-pins {
1157 drive-strength = <2>;
1158 bias-disable;
1162 blsp1_i2c1_default: blsp1-i2c1-default-state {
1165 drive-strength = <2>;
1166 bias-disable;
1169 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1172 drive-strength = <2>;
1173 bias-pull-up;
1176 blsp1_i2c2_default: blsp1-i2c2-default-state {
1179 drive-strength = <2>;
1180 bias-disable;
1183 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1186 drive-strength = <2>;
1187 bias-pull-up;
1190 blsp1_i2c3_default: blsp1-i2c3-default-state {
1193 drive-strength = <2>;
1194 bias-disable;
1197 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1200 drive-strength = <2>;
1201 bias-pull-up;
1204 blsp1_i2c4_default: blsp1-i2c4-default-state {
1207 drive-strength = <2>;
1208 bias-disable;
1211 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1214 drive-strength = <2>;
1215 bias-pull-up;
1218 blsp1_i2c5_default: blsp1-i2c5-default-state {
1221 drive-strength = <2>;
1222 bias-disable;
1225 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1228 drive-strength = <2>;
1229 bias-pull-up;
1232 blsp1_i2c6_default: blsp1-i2c6-default-state {
1235 drive-strength = <2>;
1236 bias-disable;
1239 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1242 drive-strength = <2>;
1243 bias-pull-up;
1246 blsp1_spi_b_default: blsp1-spi-b-default-state {
1249 drive-strength = <6>;
1250 bias-disable;
1253 blsp1_spi1_default: blsp1-spi1-default-state {
1256 drive-strength = <6>;
1257 bias-disable;
1260 blsp1_spi2_default: blsp1-spi2-default-state {
1263 drive-strength = <6>;
1264 bias-disable;
1267 blsp1_spi3_default: blsp1-spi3-default-state {
1270 drive-strength = <6>;
1271 bias-disable;
1274 blsp1_spi4_default: blsp1-spi4-default-state {
1277 drive-strength = <6>;
1278 bias-disable;
1281 blsp1_spi5_default: blsp1-spi5-default-state {
1284 drive-strength = <6>;
1285 bias-disable;
1288 blsp1_spi6_default: blsp1-spi6-default-state {
1291 drive-strength = <6>;
1292 bias-disable;
1297 blsp2_i2c1_default: blsp2-i2c1-default-state {
1300 drive-strength = <2>;
1301 bias-disable;
1304 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1307 drive-strength = <2>;
1308 bias-pull-up;
1311 blsp2_i2c2_default: blsp2-i2c2-default-state {
1314 drive-strength = <2>;
1315 bias-disable;
1318 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1321 drive-strength = <2>;
1322 bias-pull-up;
1325 blsp2_i2c3_default: blsp2-i2c3-default-state {
1328 drive-strength = <2>;
1329 bias-disable;
1332 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1335 drive-strength = <2>;
1336 bias-pull-up;
1339 blsp2_i2c4_default: blsp2-i2c4-default-state {
1342 drive-strength = <2>;
1343 bias-disable;
1346 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1349 drive-strength = <2>;
1350 bias-pull-up;
1353 blsp2_i2c5_default: blsp2-i2c5-default-state {
1356 drive-strength = <2>;
1357 bias-disable;
1360 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1363 drive-strength = <2>;
1364 bias-pull-up;
1367 blsp2_i2c6_default: blsp2-i2c6-default-state {
1370 drive-strength = <2>;
1371 bias-disable;
1374 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1377 drive-strength = <2>;
1378 bias-pull-up;
1381 blsp2_spi1_default: blsp2-spi1-default-state {
1384 drive-strength = <6>;
1385 bias-disable;
1388 blsp2_spi2_default: blsp2-spi2-default-state {
1391 drive-strength = <6>;
1392 bias-disable;
1395 blsp2_spi3_default: blsp2-spi3-default-state {
1398 drive-strength = <6>;
1399 bias-disable;
1402 blsp2_spi4_default: blsp2-spi4-default-state {
1405 drive-strength = <6>;
1406 bias-disable;
1409 blsp2_spi5_default: blsp2-spi5-default-state {
1412 drive-strength = <6>;
1413 bias-disable;
1416 blsp2_spi6_default: blsp2-spi6-default-state {
1419 drive-strength = <6>;
1420 bias-disable;
1425 compatible = "qcom,msm8998-mss-pil";
1427 reg-names = "qdsp6", "rmb";
1429 interrupts-extended =
1436 interrupt-names = "wdog", "fatal", "ready",
1437 "handover", "stop-ack",
1438 "shutdown-ack";
1448 clock-names = "iface", "bus", "mem", "gpll0_mss",
1451 qcom,smem-states = <&modem_smp2p_out 0>;
1452 qcom,smem-state-names = "stop";
1455 reset-names = "mss_restart";
1457 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1459 power-domains = <&rpmpd MSM8998_VDDCX>,
1461 power-domain-names = "cx", "mx";
1466 memory-region = <&mba_mem>;
1470 memory-region = <&mpss_mem>;
1474 memory-region = <&mdata_mem>;
1477 glink-edge {
1480 qcom,remote-pid = <1>;
1486 compatible = "qcom,adreno-540.1", "qcom,adreno";
1488 reg-names = "kgsl_3d0_reg_memory";
1496 clock-names = "iface",
1505 operating-points-v2 = <&gpu_opp_table>;
1506 power-domains = <&rpmpd MSM8998_VDDMX>;
1509 gpu_opp_table: opp-table {
1510 compatible = "operating-points-v2";
1511 opp-710000097 {
1512 opp-hz = /bits/ 64 <710000097>;
1513 opp-level = <RPM_SMD_LEVEL_TURBO>;
1514 opp-supported-hw = <0xff>;
1517 opp-670000048 {
1518 opp-hz = /bits/ 64 <670000048>;
1519 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1520 opp-supported-hw = <0xff>;
1523 opp-596000097 {
1524 opp-hz = /bits/ 64 <596000097>;
1525 opp-level = <RPM_SMD_LEVEL_NOM>;
1526 opp-supported-hw = <0xff>;
1529 opp-515000097 {
1530 opp-hz = /bits/ 64 <515000097>;
1531 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1532 opp-supported-hw = <0xff>;
1535 opp-414000000 {
1536 opp-hz = /bits/ 64 <414000000>;
1537 opp-level = <RPM_SMD_LEVEL_SVS>;
1538 opp-supported-hw = <0xff>;
1541 opp-342000000 {
1542 opp-hz = /bits/ 64 <342000000>;
1543 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1544 opp-supported-hw = <0xff>;
1547 opp-257000000 {
1548 opp-hz = /bits/ 64 <257000000>;
1549 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1550 opp-supported-hw = <0xff>;
1556 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1561 clock-names = "iface", "mem", "mem_iface";
1563 #global-interrupts = <0>;
1564 #iommu-cells = <1>;
1570 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1571 * GPU-CX for SMMU but we need both of them up for Adreno.
1577 power-domains = <&gpucc GPU_GX_GDSC>;
1581 gpucc: clock-controller@5065000 {
1582 compatible = "qcom,msm8998-gpucc";
1583 #clock-cells = <1>;
1584 #reset-cells = <1>;
1585 #power-domain-cells = <1>;
1590 clock-names = "xo",
1595 compatible = "qcom,msm8998-slpi-pas";
1598 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1603 interrupt-names = "wdog", "fatal", "ready",
1604 "handover", "stop-ack";
1606 px-supply = <&vreg_lvs2a_1p8>;
1609 clock-names = "xo";
1611 memory-region = <&slpi_mem>;
1613 qcom,smem-states = <&slpi_smp2p_out 0>;
1614 qcom,smem-state-names = "stop";
1616 power-domains = <&rpmpd MSM8998_SSCCX>;
1617 power-domain-names = "ssc_cx";
1621 glink-edge {
1624 qcom,remote-pid = <3>;
1629 stm: stm@6002000 {
1630 compatible = "arm,coresight-stm", "arm,primecell";
1633 reg-names = "stm-base", "stm-stimulus-base";
1637 clock-names = "apb_pclk", "atclk";
1639 out-ports {
1642 remote-endpoint = <&funnel0_in7>;
1649 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1654 clock-names = "apb_pclk", "atclk";
1656 out-ports {
1659 remote-endpoint =
1665 in-ports {
1666 #address-cells = <1>;
1667 #size-cells = <0>;
1672 remote-endpoint = <&stm_out>;
1679 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1684 clock-names = "apb_pclk", "atclk";
1686 out-ports {
1689 remote-endpoint =
1695 in-ports {
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1702 remote-endpoint =
1710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1715 clock-names = "apb_pclk", "atclk";
1717 out-ports {
1720 remote-endpoint =
1726 in-ports {
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1733 remote-endpoint =
1741 remote-endpoint =
1749 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1754 clock-names = "apb_pclk", "atclk";
1756 out-ports {
1759 remote-endpoint = <&etr_in>;
1764 in-ports {
1767 remote-endpoint = <&etf_out>;
1774 compatible = "arm,coresight-tmc", "arm,primecell";
1779 clock-names = "apb_pclk", "atclk";
1781 out-ports {
1784 remote-endpoint =
1790 in-ports {
1793 remote-endpoint =
1801 compatible = "arm,coresight-tmc", "arm,primecell";
1806 clock-names = "apb_pclk", "atclk";
1807 arm,scatter-gather;
1809 in-ports {
1812 remote-endpoint =
1820 compatible = "arm,coresight-etm4x", "arm,primecell";
1825 clock-names = "apb_pclk", "atclk";
1829 out-ports {
1832 remote-endpoint =
1840 compatible = "arm,coresight-etm4x", "arm,primecell";
1845 clock-names = "apb_pclk", "atclk";
1849 out-ports {
1852 remote-endpoint =
1860 compatible = "arm,coresight-etm4x", "arm,primecell";
1865 clock-names = "apb_pclk", "atclk";
1869 out-ports {
1872 remote-endpoint =
1880 compatible = "arm,coresight-etm4x", "arm,primecell";
1885 clock-names = "apb_pclk", "atclk";
1889 out-ports {
1892 remote-endpoint =
1900 compatible = "arm,coresight-etm4x", "arm,primecell";
1905 clock-names = "apb_pclk", "atclk";
1907 out-ports {
1910 remote-endpoint =
1916 in-ports {
1917 #address-cells = <1>;
1918 #size-cells = <0>;
1923 remote-endpoint =
1931 remote-endpoint =
1939 remote-endpoint =
1947 remote-endpoint =
1955 remote-endpoint =
1963 remote-endpoint =
1971 remote-endpoint =
1979 remote-endpoint =
1987 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1992 clock-names = "apb_pclk", "atclk";
1994 out-ports {
1997 remote-endpoint =
2003 in-ports {
2006 remote-endpoint =
2014 compatible = "arm,coresight-etm4x", "arm,primecell";
2019 clock-names = "apb_pclk", "atclk";
2023 out-ports {
2026 remote-endpoint = <&apss_funnel_in4>;
2033 compatible = "arm,coresight-etm4x", "arm,primecell";
2038 clock-names = "apb_pclk", "atclk";
2042 out-ports {
2045 remote-endpoint = <&apss_funnel_in5>;
2052 compatible = "arm,coresight-etm4x", "arm,primecell";
2057 clock-names = "apb_pclk", "atclk";
2061 out-ports {
2064 remote-endpoint = <&apss_funnel_in6>;
2071 compatible = "arm,coresight-etm4x", "arm,primecell";
2076 clock-names = "apb_pclk", "atclk";
2080 out-ports {
2083 remote-endpoint = <&apss_funnel_in7>;
2090 compatible = "qcom,rpm-stats";
2095 compatible = "qcom,spmi-pmic-arb";
2101 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2102 interrupt-names = "periph_irq";
2106 #address-cells = <2>;
2107 #size-cells = <0>;
2108 interrupt-controller;
2109 #interrupt-cells = <4>;
2113 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2116 #address-cells = <1>;
2117 #size-cells = <1>;
2125 clock-names = "cfg_noc",
2131 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2133 assigned-clock-rates = <19200000>, <120000000>;
2137 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2139 power-domains = <&gcc USB_30_GDSC>;
2150 phy-names = "usb2-phy", "usb3-phy";
2151 snps,has-lpm-erratum;
2152 snps,hird-threshold = /bits/ 8 <0x10>;
2157 compatible = "qcom,msm8998-qmp-usb3-phy";
2164 clock-names = "aux",
2168 clock-output-names = "usb3_phy_pipe_clk_src";
2169 #clock-cells = <0>;
2170 #phy-cells = <0>;
2174 reset-names = "phy",
2181 compatible = "qcom,msm8998-qusb2-phy";
2184 #phy-cells = <0>;
2188 clock-names = "cfg_ahb", "ref";
2192 nvmem-cells = <&qusb2_hstx_trim>;
2196 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2198 reg-names = "hc", "core";
2202 interrupt-names = "hc_irq", "pwr_irq";
2204 clock-names = "iface", "core", "xo";
2208 bus-width = <4>;
2212 blsp1_dma: dma-controller@c144000 {
2213 compatible = "qcom,bam-v1.7.0";
2217 clock-names = "bam_clk";
2218 #dma-cells = <1>;
2220 qcom,controlled-remotely;
2221 num-channels = <18>;
2222 qcom,num-ees = <4>;
2226 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2231 clock-names = "core", "iface";
2233 dma-names = "tx", "rx";
2234 pinctrl-names = "default";
2235 pinctrl-0 = <&blsp1_uart3_on>;
2240 compatible = "qcom,i2c-qup-v2.2.1";
2246 clock-names = "core", "iface";
2248 dma-names = "tx", "rx";
2249 pinctrl-names = "default", "sleep";
2250 pinctrl-0 = <&blsp1_i2c1_default>;
2251 pinctrl-1 = <&blsp1_i2c1_sleep>;
2252 clock-frequency = <400000>;
2255 #address-cells = <1>;
2256 #size-cells = <0>;
2260 compatible = "qcom,i2c-qup-v2.2.1";
2266 clock-names = "core", "iface";
2268 dma-names = "tx", "rx";
2269 pinctrl-names = "default", "sleep";
2270 pinctrl-0 = <&blsp1_i2c2_default>;
2271 pinctrl-1 = <&blsp1_i2c2_sleep>;
2272 clock-frequency = <400000>;
2275 #address-cells = <1>;
2276 #size-cells = <0>;
2280 compatible = "qcom,i2c-qup-v2.2.1";
2286 clock-names = "core", "iface";
2288 dma-names = "tx", "rx";
2289 pinctrl-names = "default", "sleep";
2290 pinctrl-0 = <&blsp1_i2c3_default>;
2291 pinctrl-1 = <&blsp1_i2c3_sleep>;
2292 clock-frequency = <400000>;
2295 #address-cells = <1>;
2296 #size-cells = <0>;
2300 compatible = "qcom,i2c-qup-v2.2.1";
2306 clock-names = "core", "iface";
2308 dma-names = "tx", "rx";
2309 pinctrl-names = "default", "sleep";
2310 pinctrl-0 = <&blsp1_i2c4_default>;
2311 pinctrl-1 = <&blsp1_i2c4_sleep>;
2312 clock-frequency = <400000>;
2315 #address-cells = <1>;
2316 #size-cells = <0>;
2320 compatible = "qcom,i2c-qup-v2.2.1";
2326 clock-names = "core", "iface";
2328 dma-names = "tx", "rx";
2329 pinctrl-names = "default", "sleep";
2330 pinctrl-0 = <&blsp1_i2c5_default>;
2331 pinctrl-1 = <&blsp1_i2c5_sleep>;
2332 clock-frequency = <400000>;
2335 #address-cells = <1>;
2336 #size-cells = <0>;
2340 compatible = "qcom,i2c-qup-v2.2.1";
2346 clock-names = "core", "iface";
2348 dma-names = "tx", "rx";
2349 pinctrl-names = "default", "sleep";
2350 pinctrl-0 = <&blsp1_i2c6_default>;
2351 pinctrl-1 = <&blsp1_i2c6_sleep>;
2352 clock-frequency = <400000>;
2355 #address-cells = <1>;
2356 #size-cells = <0>;
2360 compatible = "qcom,spi-qup-v2.2.1";
2366 clock-names = "core", "iface";
2368 dma-names = "tx", "rx";
2369 pinctrl-names = "default";
2370 pinctrl-0 = <&blsp1_spi1_default>;
2373 #address-cells = <1>;
2374 #size-cells = <0>;
2378 compatible = "qcom,spi-qup-v2.2.1";
2384 clock-names = "core", "iface";
2386 dma-names = "tx", "rx";
2387 pinctrl-names = "default";
2388 pinctrl-0 = <&blsp1_spi2_default>;
2391 #address-cells = <1>;
2392 #size-cells = <0>;
2396 compatible = "qcom,spi-qup-v2.2.1";
2402 clock-names = "core", "iface";
2404 dma-names = "tx", "rx";
2405 pinctrl-names = "default";
2406 pinctrl-0 = <&blsp1_spi3_default>;
2409 #address-cells = <1>;
2410 #size-cells = <0>;
2414 compatible = "qcom,spi-qup-v2.2.1";
2420 clock-names = "core", "iface";
2422 dma-names = "tx", "rx";
2423 pinctrl-names = "default";
2424 pinctrl-0 = <&blsp1_spi4_default>;
2427 #address-cells = <1>;
2428 #size-cells = <0>;
2432 compatible = "qcom,spi-qup-v2.2.1";
2438 clock-names = "core", "iface";
2440 dma-names = "tx", "rx";
2441 pinctrl-names = "default";
2442 pinctrl-0 = <&blsp1_spi5_default>;
2445 #address-cells = <1>;
2446 #size-cells = <0>;
2450 compatible = "qcom,spi-qup-v2.2.1";
2456 clock-names = "core", "iface";
2458 dma-names = "tx", "rx";
2459 pinctrl-names = "default";
2460 pinctrl-0 = <&blsp1_spi6_default>;
2463 #address-cells = <1>;
2464 #size-cells = <0>;
2467 blsp2_dma: dma-controller@c184000 {
2468 compatible = "qcom,bam-v1.7.0";
2472 clock-names = "bam_clk";
2473 #dma-cells = <1>;
2475 qcom,controlled-remotely;
2476 num-channels = <18>;
2477 qcom,num-ees = <4>;
2481 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2486 clock-names = "core", "iface";
2491 compatible = "qcom,i2c-qup-v2.2.1";
2497 clock-names = "core", "iface";
2499 dma-names = "tx", "rx";
2500 pinctrl-names = "default", "sleep";
2501 pinctrl-0 = <&blsp2_i2c1_default>;
2502 pinctrl-1 = <&blsp2_i2c1_sleep>;
2503 clock-frequency = <400000>;
2506 #address-cells = <1>;
2507 #size-cells = <0>;
2511 compatible = "qcom,i2c-qup-v2.2.1";
2517 clock-names = "core", "iface";
2519 dma-names = "tx", "rx";
2520 pinctrl-names = "default", "sleep";
2521 pinctrl-0 = <&blsp2_i2c2_default>;
2522 pinctrl-1 = <&blsp2_i2c2_sleep>;
2523 clock-frequency = <400000>;
2526 #address-cells = <1>;
2527 #size-cells = <0>;
2531 compatible = "qcom,i2c-qup-v2.2.1";
2537 clock-names = "core", "iface";
2539 dma-names = "tx", "rx";
2540 pinctrl-names = "default", "sleep";
2541 pinctrl-0 = <&blsp2_i2c3_default>;
2542 pinctrl-1 = <&blsp2_i2c3_sleep>;
2543 clock-frequency = <400000>;
2546 #address-cells = <1>;
2547 #size-cells = <0>;
2551 compatible = "qcom,i2c-qup-v2.2.1";
2557 clock-names = "core", "iface";
2559 dma-names = "tx", "rx";
2560 pinctrl-names = "default", "sleep";
2561 pinctrl-0 = <&blsp2_i2c4_default>;
2562 pinctrl-1 = <&blsp2_i2c4_sleep>;
2563 clock-frequency = <400000>;
2566 #address-cells = <1>;
2567 #size-cells = <0>;
2571 compatible = "qcom,i2c-qup-v2.2.1";
2577 clock-names = "core", "iface";
2579 dma-names = "tx", "rx";
2580 pinctrl-names = "default", "sleep";
2581 pinctrl-0 = <&blsp2_i2c5_default>;
2582 pinctrl-1 = <&blsp2_i2c5_sleep>;
2583 clock-frequency = <400000>;
2586 #address-cells = <1>;
2587 #size-cells = <0>;
2591 compatible = "qcom,i2c-qup-v2.2.1";
2597 clock-names = "core", "iface";
2599 dma-names = "tx", "rx";
2600 pinctrl-names = "default", "sleep";
2601 pinctrl-0 = <&blsp2_i2c6_default>;
2602 pinctrl-1 = <&blsp2_i2c6_sleep>;
2603 clock-frequency = <400000>;
2606 #address-cells = <1>;
2607 #size-cells = <0>;
2611 compatible = "qcom,spi-qup-v2.2.1";
2617 clock-names = "core", "iface";
2619 dma-names = "tx", "rx";
2620 pinctrl-names = "default";
2621 pinctrl-0 = <&blsp2_spi1_default>;
2624 #address-cells = <1>;
2625 #size-cells = <0>;
2629 compatible = "qcom,spi-qup-v2.2.1";
2635 clock-names = "core", "iface";
2637 dma-names = "tx", "rx";
2638 pinctrl-names = "default";
2639 pinctrl-0 = <&blsp2_spi2_default>;
2642 #address-cells = <1>;
2643 #size-cells = <0>;
2647 compatible = "qcom,spi-qup-v2.2.1";
2653 clock-names = "core", "iface";
2655 dma-names = "tx", "rx";
2656 pinctrl-names = "default";
2657 pinctrl-0 = <&blsp2_spi3_default>;
2660 #address-cells = <1>;
2661 #size-cells = <0>;
2665 compatible = "qcom,spi-qup-v2.2.1";
2671 clock-names = "core", "iface";
2673 dma-names = "tx", "rx";
2674 pinctrl-names = "default";
2675 pinctrl-0 = <&blsp2_spi4_default>;
2678 #address-cells = <1>;
2679 #size-cells = <0>;
2683 compatible = "qcom,spi-qup-v2.2.1";
2689 clock-names = "core", "iface";
2691 dma-names = "tx", "rx";
2692 pinctrl-names = "default";
2693 pinctrl-0 = <&blsp2_spi5_default>;
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2701 compatible = "qcom,spi-qup-v2.2.1";
2707 clock-names = "core", "iface";
2709 dma-names = "tx", "rx";
2710 pinctrl-names = "default";
2711 pinctrl-0 = <&blsp2_spi6_default>;
2714 #address-cells = <1>;
2715 #size-cells = <0>;
2718 mmcc: clock-controller@c8c0000 {
2719 compatible = "qcom,mmcc-msm8998";
2720 #clock-cells = <1>;
2721 #reset-cells = <1>;
2722 #power-domain-cells = <1>;
2725 clock-names = "xo",
2747 mdss: display-subsystem@c900000 {
2748 compatible = "qcom,msm8998-mdss";
2750 reg-names = "mdss";
2753 interrupt-controller;
2754 #interrupt-cells = <1>;
2759 clock-names = "iface",
2763 power-domains = <&mmcc MDSS_GDSC>;
2766 #address-cells = <1>;
2767 #size-cells = <1>;
2772 mdss_mdp: display-controller@c901000 {
2773 compatible = "qcom,msm8998-dpu";
2778 reg-names = "mdp",
2783 interrupt-parent = <&mdss>;
2791 clock-names = "iface",
2797 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2798 assigned-clock-rates = <19200000>;
2800 operating-points-v2 = <&mdp_opp_table>;
2801 power-domains = <&rpmpd MSM8998_VDDMX>;
2803 mdp_opp_table: opp-table {
2804 compatible = "operating-points-v2";
2806 opp-171430000 {
2807 opp-hz = /bits/ 64 <171430000>;
2808 required-opps = <&rpmpd_opp_low_svs>;
2811 opp-275000000 {
2812 opp-hz = /bits/ 64 <275000000>;
2813 required-opps = <&rpmpd_opp_svs>;
2816 opp-330000000 {
2817 opp-hz = /bits/ 64 <330000000>;
2818 required-opps = <&rpmpd_opp_nom>;
2821 opp-412500000 {
2822 opp-hz = /bits/ 64 <412500000>;
2823 required-opps = <&rpmpd_opp_turbo>;
2828 #address-cells = <1>;
2829 #size-cells = <0>;
2835 remote-endpoint = <&mdss_dsi0_in>;
2843 remote-endpoint = <&mdss_dsi1_in>;
2850 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2852 reg-names = "dsi_ctrl";
2854 interrupt-parent = <&mdss>;
2863 clock-names = "byte",
2869 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2871 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2874 operating-points-v2 = <&dsi_opp_table>;
2875 power-domains = <&rpmpd MSM8998_VDDCX>;
2878 phy-names = "dsi";
2880 #address-cells = <1>;
2881 #size-cells = <0>;
2886 #address-cells = <1>;
2887 #size-cells = <0>;
2893 remote-endpoint = <&dpu_intf1_out>;
2907 compatible = "qcom,dsi-phy-10nm-8998";
2911 reg-names = "dsi_phy",
2917 clock-names = "iface", "ref";
2919 #clock-cells = <1>;
2920 #phy-cells = <0>;
2926 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2928 reg-names = "dsi_ctrl";
2930 interrupt-parent = <&mdss>;
2939 clock-names = "byte",
2945 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2947 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2950 operating-points-v2 = <&dsi_opp_table>;
2951 power-domains = <&rpmpd MSM8998_VDDCX>;
2954 phy-names = "dsi";
2956 #address-cells = <1>;
2957 #size-cells = <0>;
2962 #address-cells = <1>;
2963 #size-cells = <0>;
2969 remote-endpoint = <&dpu_intf2_out>;
2983 compatible = "qcom,dsi-phy-10nm-8998";
2987 reg-names = "dsi_phy",
2993 clock-names = "iface",
2996 #clock-cells = <1>;
2997 #phy-cells = <0>;
3004 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3006 #iommu-cells = <1>;
3011 clock-names = "iface-mm",
3012 "iface-smmu",
3013 "bus-smmu";
3015 #global-interrupts = <0>;
3038 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3042 compatible = "qcom,msm8998-adsp-pas";
3045 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3050 interrupt-names = "wdog", "fatal", "ready",
3051 "handover", "stop-ack";
3054 clock-names = "xo";
3056 memory-region = <&adsp_mem>;
3058 qcom,smem-states = <&adsp_smp2p_out 0>;
3059 qcom,smem-state-names = "stop";
3061 power-domains = <&rpmpd MSM8998_VDDCX>;
3062 power-domain-names = "cx";
3066 glink-edge {
3069 qcom,remote-pid = <2>;
3075 compatible = "qcom,msm8998-apcs-hmss-global",
3076 "qcom,msm8994-apcs-kpss-global";
3079 #mbox-cells = <1>;
3083 #address-cells = <1>;
3084 #size-cells = <1>;
3086 compatible = "arm,armv7-timer-mem";
3090 frame-number = <0>;
3098 frame-number = <1>;
3105 frame-number = <2>;
3112 frame-number = <3>;
3119 frame-number = <4>;
3126 frame-number = <5>;
3133 frame-number = <6>;
3140 intc: interrupt-controller@17a00000 {
3141 compatible = "arm,gic-v3";
3144 #interrupt-cells = <3>;
3145 #address-cells = <1>;
3146 #size-cells = <1>;
3148 interrupt-controller;
3149 #redistributor-regions = <1>;
3150 redistributor-stride = <0x0 0x20000>;
3155 compatible = "qcom,wcn3990-wifi";
3158 reg-names = "membase";
3159 memory-region = <&wlan_msa_mem>;
3161 clock-names = "cxo_ref_clk_pin";
3177 qcom,snoc-host-cap-8bit-quirk;