Lines Matching +full:stm +full:- +full:base
1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
72 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
74 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
78 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
80 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
84 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
88 APInt apIntN = N->getAPIntValue();
90 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
93 // t2_so_imm - Match a 32-bit immediate operand, which is an
94 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
102 return ARM_AM::getT2SOImmVal(Imm) != -1;
109 // t2_so_imm_not - Match an immediate that is a complement
116 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
121 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
124 APInt apIntN = N->getAPIntValue();
127 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
132 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
135 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
140 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
150 return (uint32_t)(-N->getZExtValue()) < 4096;
156 uint32_t Val = -N->getZExtValue();
161 return (uint32_t)(~N->getZExtValue()) < 255;
165 // Returns true if all low 5-bits are 1.
166 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
178 let MIOperandInfo = (ops GPRnopc:$base);
188 let MIOperandInfo = (ops rGPR:$base);
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
231 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
234 // t2addrmode_negimm8 := reg - imm8
245 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
248 // t2addrmode_imm8 := reg +/- imm8
258 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
277 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
284 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
302 // t2addrmode_imm7s4 := reg +/- (imm7 << 2)
308 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
340 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
351 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
368 // Define ARMv8.1-M specific addressing modes.
437 //===----------------------------------------------------------------------===//
448 let Inst{11-8} = Rd;
450 let Inst{14-12} = imm{10-8};
451 let Inst{7-0} = imm{7-0};
462 let Inst{11-8} = Rd;
464 let Inst{14-12} = imm{10-8};
465 let Inst{7-0} = imm{7-0};
474 let Inst{19-16} = Rn;
476 let Inst{14-12} = imm{10-8};
477 let Inst{7-0} = imm{7-0};
487 let Inst{11-8} = Rd;
488 let Inst{3-0} = ShiftedRm{3-0};
489 let Inst{5-4} = ShiftedRm{6-5};
490 let Inst{14-12} = ShiftedRm{11-9};
491 let Inst{7-6} = ShiftedRm{8-7};
500 let Inst{11-8} = Rd;
501 let Inst{3-0} = ShiftedRm{3-0};
502 let Inst{5-4} = ShiftedRm{6-5};
503 let Inst{14-12} = ShiftedRm{11-9};
504 let Inst{7-6} = ShiftedRm{8-7};
513 let Inst{19-16} = Rn;
514 let Inst{3-0} = ShiftedRm{3-0};
515 let Inst{5-4} = ShiftedRm{6-5};
516 let Inst{14-12} = ShiftedRm{11-9};
517 let Inst{7-6} = ShiftedRm{8-7};
526 let Inst{11-8} = Rd;
527 let Inst{3-0} = Rm;
536 let Inst{11-8} = Rd;
537 let Inst{3-0} = Rm;
546 let Inst{19-16} = Rn;
547 let Inst{3-0} = Rm;
558 let Inst{11-8} = Rd;
559 let Inst{19-16} = Rn;
561 let Inst{14-12} = imm{10-8};
562 let Inst{7-0} = imm{7-0};
572 let Inst{11-8} = Rd;
573 let Inst{19-16} = Rn;
575 let Inst{14-12} = imm{10-8};
576 let Inst{7-0} = imm{7-0};
586 let Inst{11-8} = Rd;
587 let Inst{3-0} = Rm;
588 let Inst{14-12} = imm{4-2};
589 let Inst{7-6} = imm{1-0};
599 let Inst{11-8} = Rd;
600 let Inst{3-0} = Rm;
601 let Inst{14-12} = imm{4-2};
602 let Inst{7-6} = imm{1-0};
612 let Inst{11-8} = Rd;
613 let Inst{19-16} = Rn;
614 let Inst{3-0} = Rm;
624 let Inst{11-8} = Rd;
625 let Inst{19-16} = Rn;
626 let Inst{3-0} = Rm;
636 let Inst{11-8} = Rd;
637 let Inst{19-16} = Rn;
638 let Inst{3-0} = Rm;
648 let Inst{11-8} = Rd;
649 let Inst{19-16} = Rn;
650 let Inst{3-0} = ShiftedRm{3-0};
651 let Inst{5-4} = ShiftedRm{6-5};
652 let Inst{14-12} = ShiftedRm{11-9};
653 let Inst{7-6} = ShiftedRm{8-7};
663 let Inst{11-8} = Rd;
664 let Inst{19-16} = Rn;
665 let Inst{3-0} = ShiftedRm{3-0};
666 let Inst{5-4} = ShiftedRm{6-5};
667 let Inst{14-12} = ShiftedRm{11-9};
668 let Inst{7-6} = ShiftedRm{8-7};
679 let Inst{19-16} = Rn;
680 let Inst{15-12} = Ra;
681 let Inst{11-8} = Rd;
682 let Inst{3-0} = Rm;
695 let Inst{31-23} = 0b111110111;
696 let Inst{22-20} = opc22_20;
697 let Inst{19-16} = Rn;
698 let Inst{15-12} = RdLo;
699 let Inst{11-8} = RdHi;
700 let Inst{7-4} = opc7_4;
701 let Inst{3-0} = Rm;
714 let Inst{31-23} = 0b111110111;
715 let Inst{22-20} = opc22_20;
716 let Inst{19-16} = Rn;
717 let Inst{15-12} = RdLo;
718 let Inst{11-8} = RdHi;
719 let Inst{7-4} = opc7_4;
720 let Inst{3-0} = Rm;
724 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
737 let Inst{31-27} = 0b11110;
739 let Inst{24-21} = opcod;
748 let Inst{31-27} = 0b11101;
749 let Inst{26-25} = 0b01;
750 let Inst{24-21} = opcod;
754 // than 0, i.e. setting it to 1 is UNPREDICTABLE or a soft-fail
755 // rather than a hard failure. In v8.1-M, this requirement is
759 // that encoding clash in the auto- generated MC decoder, so I
762 let Inst{14-12} = 0b000; // imm3
763 let Inst{7-6} = 0b00; // imm2
764 let Inst{5-4} = 0b00; // type
772 let Inst{31-27} = 0b11101;
773 let Inst{26-25} = 0b01;
774 let Inst{24-21} = opcod;
794 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
824 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
834 let Inst{31-27} = 0b11110;
836 let Inst{24-21} = opcod;
845 let Inst{31-27} = 0b11101;
846 let Inst{26-25} = 0b01;
847 let Inst{24-21} = opcod;
848 let Inst{14-12} = 0b000; // imm3
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
858 let Inst{31-27} = 0b11101;
859 let Inst{26-25} = 0b01;
860 let Inst{24-21} = opcod;
864 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
867 /// These opcodes will be converted to the real non-S opcodes by
898 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
919 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
924 // The register-immediate version is re-materializable. This is useful
935 let Inst{31-27} = 0b11110;
936 let Inst{25-24} = 0b01;
937 let Inst{23-21} = op23_21;
948 let Inst{31-27} = 0b11110;
951 let Inst{23-21} = op23_21;
955 // 12-bit imm
964 let Inst{31-27} = 0b11110;
966 let Inst{25-24} = 0b10;
967 let Inst{23-21} = op23_21;
969 let Inst{19-16} = Rn;
971 let Inst{14-12} = imm{10-8};
972 let Inst{11-8} = Rd;
973 let Inst{7-0} = imm{7-0};
983 let Inst{31-27} = 0b11110;
985 let Inst{25-24} = 0b10;
986 let Inst{23-21} = op23_21;
988 let Inst{19-16} = Rn;
990 let Inst{14-12} = imm{10-8};
991 let Inst{11-8} = Rd;
992 let Inst{7-0} = imm{7-0};
1001 let Inst{31-27} = 0b11101;
1002 let Inst{26-25} = 0b01;
1004 let Inst{23-21} = op23_21;
1005 let Inst{14-12} = 0b000; // imm3
1006 let Inst{7-6} = 0b00; // imm2
1007 let Inst{5-4} = 0b00; // type
1015 let Inst{31-27} = 0b11101;
1016 let Inst{26-25} = 0b01;
1018 let Inst{23-21} = op23_21;
1022 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
1033 let Inst{31-27} = 0b11110;
1035 let Inst{24-21} = opcod;
1044 let Inst{31-27} = 0b11101;
1045 let Inst{26-25} = 0b01;
1046 let Inst{24-21} = opcod;
1047 let Inst{14-12} = 0b000; // imm3
1048 let Inst{7-6} = 0b00; // imm2
1049 let Inst{5-4} = 0b00; // type
1057 let Inst{31-27} = 0b11101;
1058 let Inst{26-25} = 0b01;
1059 let Inst{24-21} = opcod;
1083 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
1086 // 5-bit imm
1092 let Inst{31-27} = 0b11101;
1093 let Inst{26-21} = 0b010010;
1094 let Inst{19-16} = 0b1111; // Rn
1096 let Inst{5-4} = opcod;
1104 let Inst{31-27} = 0b11111;
1105 let Inst{26-23} = 0b0100;
1106 let Inst{22-21} = opcod;
1107 let Inst{15-12} = 0b1111;
1108 let Inst{7-4} = 0b0000;
1136 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1148 let Inst{31-27} = 0b11110;
1150 let Inst{24-21} = opcod;
1153 let Inst{11-8} = 0b1111; // Rd
1160 let Inst{31-27} = 0b11101;
1161 let Inst{26-25} = 0b01;
1162 let Inst{24-21} = opcod;
1164 let Inst{14-12} = 0b000; // imm3
1165 let Inst{11-8} = 0b1111; // Rd
1166 let Inst{7-6} = 0b00; // imm2
1167 let Inst{5-4} = 0b00; // type
1175 let Inst{31-27} = 0b11101;
1176 let Inst{26-25} = 0b01;
1177 let Inst{24-21} = opcod;
1179 let Inst{11-8} = 0b1111; // Rd
1192 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1202 let Inst{31-25} = 0b1111100;
1205 let Inst{22-21} = opcod;
1207 let Inst{19-16} = addr{16-13}; // Rn
1208 let Inst{15-12} = Rt;
1209 let Inst{11-0} = addr{11-0}; // imm
1219 let Inst{31-27} = 0b11111;
1220 let Inst{26-25} = 0b00;
1223 let Inst{22-21} = opcod;
1225 let Inst{19-16} = addr{12-9}; // Rn
1226 let Inst{15-12} = Rt;
1232 let Inst{7-0} = addr{7-0}; // imm
1240 let Inst{31-27} = 0b11111;
1241 let Inst{26-25} = 0b00;
1244 let Inst{22-21} = opcod;
1246 let Inst{11-6} = 0b000000;
1249 let Inst{15-12} = Rt;
1252 let Inst{19-16} = addr{9-6}; // Rn
1253 let Inst{3-0} = addr{5-2}; // Rm
1254 let Inst{5-4} = addr{1-0}; // imm
1266 let Inst{31-27} = 0b11111;
1267 let Inst{26-25} = 0b00;
1269 let Inst{22-21} = opcod;
1271 let Inst{19-16} = 0b1111; // Rn
1274 let Inst{15-12} = Rt{3-0};
1278 let Inst{11-0} = addr{11-0};
1284 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1292 let Inst{31-27} = 0b11111;
1293 let Inst{26-23} = 0b0001;
1294 let Inst{22-21} = opcod;
1298 let Inst{15-12} = Rt;
1302 let Inst{19-16} = addr{16-13}; // Rn
1304 let Inst{11-0} = addr{11-0}; // imm
1310 let Inst{31-27} = 0b11111;
1311 let Inst{26-23} = 0b0000;
1312 let Inst{22-21} = opcod;
1320 let Inst{15-12} = Rt;
1323 let Inst{19-16} = addr{12-9}; // Rn
1325 let Inst{7-0} = addr{7-0}; // imm
1331 let Inst{31-27} = 0b11111;
1332 let Inst{26-23} = 0b0000;
1333 let Inst{22-21} = opcod;
1335 let Inst{11-6} = 0b000000;
1338 let Inst{15-12} = Rt;
1341 let Inst{19-16} = addr{9-6}; // Rn
1342 let Inst{3-0} = addr{5-2}; // Rm
1343 let Inst{5-4} = addr{1-0}; // imm
1347 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1354 let Inst{31-27} = 0b11111;
1355 let Inst{26-23} = 0b0100;
1356 let Inst{22-20} = opcod;
1357 let Inst{19-16} = 0b1111; // Rn
1358 let Inst{15-12} = 0b1111;
1360 let Inst{5-4} = rot; // rotate
1371 // UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
1380 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1389 let Inst{31-27} = 0b11111;
1390 let Inst{26-23} = 0b0100;
1391 let Inst{22-20} = opcod;
1392 let Inst{15-12} = 0b1111;
1394 let Inst{5-4} = rot;
1397 //===----------------------------------------------------------------------===//
1399 //===----------------------------------------------------------------------===//
1401 //===----------------------------------------------------------------------===//
1411 let Inst{11-8} = Rd;
1413 let Inst{14-12} = label{10-8};
1414 let Inst{7-0} = label{7-0};
1417 // LEApcrel - Load a pc-relative address into a register without offending the
1423 let Inst{31-27} = 0b11110;
1424 let Inst{25-24} = 0b10;
1428 let Inst{19-16} = 0b1111; // Rn
1433 let Inst{11-8} = Rd;
1437 let Inst{14-12} = addr{10-8};
1438 let Inst{7-0} = addr{7-0};
1453 //===----------------------------------------------------------------------===//
1482 // zextload i1 -> zextload i8
1492 // extload -> zextload
1533 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1545 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1557 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1569 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1581 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1593 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1601 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1611 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1621 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1631 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1646 let Inst{31-27} = 0b11111;
1647 let Inst{26-25} = 0b00;
1650 let Inst{22-21} = type;
1652 let Inst{19-16} = addr{12-9};
1653 let Inst{15-12} = Rt;
1655 let Inst{10-8} = 0b110; // PUW.
1656 let Inst{7-0} = addr{7-0};
1674 let Inst{31-27} = 0b11101;
1675 let Inst{26-24} = 0b000;
1676 let Inst{23-20} = bits23_20;
1677 let Inst{11-6} = 0b111110;
1678 let Inst{5-4} = bit54;
1679 let Inst{3-0} = 0b1111;
1682 let Inst{19-16} = addr;
1683 let Inst{15-12} = Rt;
1718 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1725 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1732 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1769 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1771 // the address base and offset to be separate operands, not a single
1799 // "$addr.base = $Rn_wb,@earlyclobber $Rn_wb" on PRE.
1807 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1817 // "$Rn = $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
1831 let Inst{31-27} = 0b11111;
1832 let Inst{26-25} = 0b00;
1835 let Inst{22-21} = type;
1838 let Inst{10-8} = 0b110; // PUW
1842 let Inst{15-12} = Rt;
1843 let Inst{19-16} = addr{12-9};
1844 let Inst{7-0} = addr{7-0};
1856 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1865 "$addr.base = $wb", []>, Sched<[WriteLd]>;
1871 "$addr.base = $wb", []>, Sched<[WriteST]> {
1880 "$addr.base = $wb", []>, Sched<[WriteST]>;
1890 let Inst{31-27} = 0b11101;
1891 let Inst{26-20} = 0b0001100;
1892 let Inst{11-6} = 0b111110;
1893 let Inst{5-4} = bit54;
1894 let Inst{3-0} = 0b1111;
1897 let Inst{19-16} = addr;
1898 let Inst{15-12} = Rt;
1910 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1911 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1918 let Inst{31-25} = 0b1111100;
1924 let Inst{15-12} = 0b1111;
1927 let Inst{19-16} = addr{16-13}; // Rn
1928 let Inst{11-0} = addr{11-0}; // imm12
1937 let Inst{31-25} = 0b1111100;
1943 let Inst{15-12} = 0b1111;
1944 let Inst{11-8} = 0b1100;
1947 let Inst{19-16} = addr{12-9}; // Rn
1948 let Inst{7-0} = addr{7-0}; // imm8
1957 let Inst{31-25} = 0b1111100;
1963 let Inst{15-12} = 0b1111;
1964 let Inst{11-6} = 0b000000;
1967 let Inst{19-16} = addr{9-6}; // Rn
1968 let Inst{3-0} = addr{5-2}; // Rm
1969 let Inst{5-4} = addr{1-0}; // imm2
2013 let Inst{31-25} = 0b1111100;
2015 let Inst{22-20} = 0b001;
2016 let Inst{19-16} = 0b1111;
2017 let Inst{15-12} = 0b1111;
2021 let Inst{11-0} = addr{11-0}; // imm12
2047 //===----------------------------------------------------------------------===//
2059 let Inst{31-27} = 0b11101;
2060 let Inst{26-25} = 0b00;
2061 let Inst{24-23} = 0b01; // Increment After
2065 let Inst{19-16} = Rn;
2066 let Inst{15-0} = regs;
2074 let Inst{31-27} = 0b11101;
2075 let Inst{26-25} = 0b00;
2076 let Inst{24-23} = 0b01; // Increment After
2080 let Inst{19-16} = Rn;
2081 let Inst{15-0} = regs;
2089 let Inst{31-27} = 0b11101;
2090 let Inst{26-25} = 0b00;
2091 let Inst{24-23} = 0b10; // Decrement Before
2095 let Inst{19-16} = Rn;
2096 let Inst{15-0} = regs;
2104 let Inst{31-27} = 0b11101;
2105 let Inst{26-25} = 0b00;
2106 let Inst{24-23} = 0b10; // Decrement Before
2110 let Inst{19-16} = Rn;
2111 let Inst{15-0} = regs;
2128 let Inst{31-27} = 0b11101;
2129 let Inst{26-25} = 0b00;
2130 let Inst{24-23} = 0b01; // Increment After
2134 let Inst{19-16} = Rn;
2138 let Inst{12-0} = regs{12-0};
2146 let Inst{31-27} = 0b11101;
2147 let Inst{26-25} = 0b00;
2148 let Inst{24-23} = 0b01; // Increment After
2152 let Inst{19-16} = Rn;
2156 let Inst{12-0} = regs{12-0};
2164 let Inst{31-27} = 0b11101;
2165 let Inst{26-25} = 0b00;
2166 let Inst{24-23} = 0b10; // Decrement Before
2170 let Inst{19-16} = Rn;
2174 let Inst{12-0} = regs{12-0};
2182 let Inst{31-27} = 0b11101;
2183 let Inst{26-25} = 0b00;
2184 let Inst{24-23} = 0b10; // Decrement Before
2188 let Inst{19-16} = Rn;
2192 let Inst{12-0} = regs{12-0};
2198 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
2203 //===----------------------------------------------------------------------===//
2210 let Inst{31-27} = 0b11101;
2211 let Inst{26-25} = 0b01;
2212 let Inst{24-21} = 0b0010;
2213 let Inst{19-16} = 0b1111; // Rn
2215 let Inst{14-12} = 0b000;
2216 let Inst{7-4} = 0b0000;
2231 let Inst{31-27} = 0b11110;
2233 let Inst{24-21} = 0b0010;
2234 let Inst{19-16} = 0b1111; // Rn
2255 let Inst{31-27} = 0b11110;
2257 let Inst{24-21} = 0b0010;
2264 let Inst{11-8} = Rd;
2265 let Inst{19-16} = imm{15-12};
2267 let Inst{14-12} = imm{10-8};
2268 let Inst{7-0} = imm{7-0};
2276 // This gets lowered to a single 4-byte instructions
2290 let Inst{31-27} = 0b11110;
2292 let Inst{24-21} = 0b0110;
2299 let Inst{11-8} = Rd;
2300 let Inst{19-16} = imm{15-12};
2302 let Inst{14-12} = imm{10-8};
2303 let Inst{7-0} = imm{7-0};
2307 // This gets lowered to a single 4-byte instructions
2316 //===----------------------------------------------------------------------===//
2350 // A simple right-shift can also be used in most cases (the exception is the
2351 // SXTH operations with a rotate of 24: there the non-contiguous bits are
2420 //===----------------------------------------------------------------------===//
2428 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2484 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2485 // The assume-no-carry-in form uses the negation of the input since add/sub
2490 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2501 // Do the same for v8m targets since they support movw with a 16-bit value.
2513 // The with-carry-in form matches bitwise not instead of the negation.
2528 let Inst{31-27} = 0b11111;
2529 let Inst{26-24} = 0b010;
2531 let Inst{22-20} = 0b010;
2532 let Inst{15-12} = 0b1111;
2534 let Inst{6-4} = 0b000;
2538 // And Miscellaneous operations -- for disassembly only
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-23} = 0b0101;
2545 let Inst{22-20} = op22_20;
2546 let Inst{15-12} = 0b1111;
2547 let Inst{7-4} = op7_4;
2553 let Inst{11-8} = Rd;
2554 let Inst{19-16} = Rn;
2555 let Inst{3-0} = Rm;
2654 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2658 let Inst{31-27} = 0b11111;
2659 let Inst{26-24} = 0b011;
2661 let Inst{22-20} = op22_20;
2662 let Inst{7-4} = op7_4;
2668 let Inst{31-27} = 0b11111;
2669 let Inst{26-24} = 0b011;
2671 let Inst{22-20} = op22_20;
2672 let Inst{7-4} = op7_4;
2681 let Inst{15-12} = 0b1111;
2697 let Inst{31-24} = 0b11110011;
2700 let Inst{19-16} = Rn;
2702 let Inst{14-12} = sh{4-2};
2703 let Inst{11-8} = Rd;
2704 let Inst{7-6} = sh{1-0};
2706 let Inst{4-0} = sat_imm;
2712 let Inst{23-22} = 0b00;
2719 let Inst{23-22} = 0b00;
2727 let Inst{23-22} = 0b10;
2733 let Inst{23-22} = 0b10;
2768 //===----------------------------------------------------------------------===//
2778 // LSL with non-zero shift
2792 let Inst{31-27} = 0b11101;
2793 let Inst{26-25} = 0b01;
2794 let Inst{24-21} = 0b0010;
2795 let Inst{19-16} = 0b1111; // Rn
2798 let Inst{14-12} = 0b000;
2799 let Inst{7-4} = 0b0011;
2809 let Inst{31-27} = 0b11101;
2810 let Inst{26-25} = 0b01;
2811 let Inst{24-21} = 0b0010;
2813 let Inst{19-16} = 0b1111; // Rn
2814 let Inst{5-4} = 0b01; // Shift type.
2815 // Shift amount = Inst{14-12:7-6} = 1.
2816 let Inst{14-12} = 0b000;
2817 let Inst{7-6} = 0b01;
2824 let Inst{31-27} = 0b11101;
2825 let Inst{26-25} = 0b01;
2826 let Inst{24-21} = 0b0010;
2828 let Inst{19-16} = 0b1111; // Rn
2829 let Inst{5-4} = 0b10; // Shift type.
2830 // Shift amount = Inst{14-12:7-6} = 1.
2831 let Inst{14-12} = 0b000;
2832 let Inst{7-6} = 0b01;
2836 //===----------------------------------------------------------------------===//
2858 let Inst{11-8} = Rd;
2859 let Inst{4-0} = msb{4-0};
2860 let Inst{14-12} = lsb{4-2};
2861 let Inst{7-6} = lsb{1-0};
2869 let Inst{19-16} = Rn;
2876 let Inst{31-27} = 0b11110;
2879 let Inst{24-20} = 0b10110;
2880 let Inst{19-16} = 0b1111; // Rn
2885 let msb{4-0} = imm{9-5};
2886 let lsb{4-0} = imm{4-0};
2892 let Inst{31-27} = 0b11110;
2894 let Inst{24-20} = 0b10100;
2903 let Inst{31-27} = 0b11110;
2905 let Inst{24-20} = 0b11100;
2911 // A8.8.247 UDF - Undefined (Encoding T2)
2915 let Inst{31-29} = 0b111;
2916 let Inst{28-27} = 0b10;
2917 let Inst{26-20} = 0b1111111;
2918 let Inst{19-16} = imm16{15-12};
2920 let Inst{14-12} = 0b010;
2921 let Inst{11-0} = imm16{11-0};
2924 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2931 let Inst{31-27} = 0b11110;
2934 let Inst{24-20} = 0b10110;
2939 let msb{4-0} = imm{9-5};
2940 let lsb{4-0} = imm{4-0};
2954 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2968 let Inst{31-27} = 0b11110;
2970 let Inst{24-21} = opcod;
2971 let Inst{19-16} = 0b1111; // Rn
2978 let Inst{31-27} = 0b11101;
2979 let Inst{26-25} = 0b01;
2980 let Inst{24-21} = opcod;
2981 let Inst{19-16} = 0b1111; // Rn
2982 let Inst{14-12} = 0b000; // imm3
2983 let Inst{7-6} = 0b00; // imm2
2984 let Inst{5-4} = 0b00; // type
2991 let Inst{31-27} = 0b11101;
2992 let Inst{26-25} = 0b01;
2993 let Inst{24-21} = opcod;
2994 let Inst{19-16} = 0b1111; // Rn
2998 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
3033 //===----------------------------------------------------------------------===//
3041 let Inst{31-27} = 0b11111;
3042 let Inst{26-23} = 0b0110;
3043 let Inst{22-20} = 0b000;
3044 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3045 let Inst{7-4} = 0b0000; // Multiply
3053 let Inst{31-27} = 0b11111;
3054 let Inst{26-23} = 0b0110;
3055 let Inst{22-20} = 0b000;
3056 let Inst{7-4} = op7_4;
3092 let Inst{31-27} = 0b11111;
3093 let Inst{26-23} = 0b0110;
3094 let Inst{22-20} = 0b101;
3095 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3096 let Inst{7-4} = op7_4;
3110 let Inst{31-27} = 0b11111;
3111 let Inst{26-23} = 0b0110;
3112 let Inst{22-20} = op22_20;
3113 let Inst{7-4} = op7_4;
3130 let Inst{31-27} = 0b11111;
3131 let Inst{26-23} = 0b0110;
3132 let Inst{22-20} = op22_20;
3133 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3134 let Inst{7-6} = 0b00;
3135 let Inst{5-4} = op5_4;
3177 let Inst{31-27} = 0b11111;
3178 let Inst{26-23} = 0b0110;
3179 let Inst{22-20} = op22_20;
3180 let Inst{7-6} = 0b00;
3181 let Inst{5-4} = op5_4;
3250 let Inst{15-12} = 0b1111;
3296 //===----------------------------------------------------------------------===//
3298 // Signed and unsigned division on v7-M
3305 let Inst{31-27} = 0b11111;
3306 let Inst{26-21} = 0b011100;
3308 let Inst{15-12} = 0b1111;
3309 let Inst{7-4} = 0b1111;
3317 let Inst{31-27} = 0b11111;
3318 let Inst{26-21} = 0b011101;
3320 let Inst{15-12} = 0b1111;
3321 let Inst{7-4} = 0b1111;
3324 //===----------------------------------------------------------------------===//
3331 let Inst{31-27} = 0b11111;
3332 let Inst{26-22} = 0b01010;
3333 let Inst{21-20} = op1;
3334 let Inst{15-12} = 0b1111;
3335 let Inst{7-6} = 0b10;
3336 let Inst{5-4} = op2;
3337 let Rn{3-0} = Rm;
3378 let Inst{31-27} = 0b11101;
3379 let Inst{26-25} = 0b01;
3380 let Inst{24-20} = 0b01100;
3385 let Inst{14-12} = sh{4-2};
3386 let Inst{7-6} = sh{1-0};
3397 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3407 let Inst{31-27} = 0b11101;
3408 let Inst{26-25} = 0b01;
3409 let Inst{24-20} = 0b01100;
3414 let Inst{14-12} = sh{4-2};
3415 let Inst{7-6} = sh{1-0};
3433 //===----------------------------------------------------------------------===//
3446 let Inst{31-27} = 0b11111;
3447 let Inst{26-21} = 0b010110;
3449 let Inst{15-12} = 0b1111;
3450 let Inst{7-6} = 0b10;
3451 let Inst{5-4} = sz;
3461 //===----------------------------------------------------------------------===//
3481 let Inst{31-27} = 0b11110;
3483 let Inst{24-21} = 0b1000;
3486 let Inst{11-8} = 0b1111; // Rd
3494 let Inst{31-27} = 0b11101;
3495 let Inst{26-25} = 0b01;
3496 let Inst{24-21} = 0b1000;
3498 let Inst{14-12} = 0b000; // imm3
3499 let Inst{11-8} = 0b1111; // Rd
3500 let Inst{7-6} = 0b00; // imm2
3501 let Inst{5-4} = 0b00; // type
3510 let Inst{31-27} = 0b11101;
3511 let Inst{26-25} = 0b01;
3512 let Inst{24-21} = 0b1000;
3514 let Inst{11-8} = 0b1111; // Rd
3605 //===----------------------------------------------------------------------===//
3615 let Inst{31-4} = 0xf3bf8f5;
3616 let Inst{3-0} = opt;
3623 let Inst{31-4} = 0xf3bf8f4;
3624 let Inst{3-0} = opt;
3631 let Inst{31-4} = 0xf3bf8f6;
3632 let Inst{3-0} = opt;
3638 let Inst{31-0} = 0xf3af8012;
3643 // Armv8.5-A speculation barrier
3646 let Inst{31-0} = 0xf3bf8f70;
3655 let Inst{31-27} = 0b11101;
3656 let Inst{26-20} = 0b0001101;
3657 let Inst{11-8} = rt2;
3658 let Inst{7-4} = opcod;
3659 let Inst{3-0} = 0b1111;
3663 let Inst{19-16} = addr;
3664 let Inst{15-12} = Rt;
3670 let Inst{31-27} = 0b11101;
3671 let Inst{26-20} = 0b0001100;
3672 let Inst{11-8} = rt2;
3673 let Inst{7-4} = opcod;
3678 let Inst{3-0} = Rd;
3679 let Inst{19-16} = addr;
3680 let Inst{15-12} = Rt;
3701 let Inst{31-27} = 0b11101;
3702 let Inst{26-20} = 0b0000101;
3703 let Inst{19-16} = addr{11-8};
3704 let Inst{15-12} = Rt;
3705 let Inst{11-8} = 0b1111;
3706 let Inst{7-0} = addr{7-0};
3716 let Inst{11-8} = Rt2;
3735 let Inst{31-27} = 0b11101;
3736 let Inst{26-20} = 0b0001101;
3737 let Inst{19-16} = addr;
3738 let Inst{15-12} = Rt;
3739 let Inst{11-8} = 0b1111;
3740 let Inst{7-0} = 0b11101111;
3750 let Inst{11-8} = Rt2;
3782 let Inst{31-27} = 0b11101;
3783 let Inst{26-20} = 0b0000100;
3784 let Inst{19-16} = addr{11-8};
3785 let Inst{15-12} = Rt;
3786 let Inst{11-8} = Rd;
3787 let Inst{7-0} = addr{7-0};
3797 let Inst{11-8} = Rt2;
3828 let Inst{31-27} = 0b11101;
3829 let Inst{26-20} = 0b0001100;
3830 let Inst{19-16} = addr;
3831 let Inst{15-12} = Rt;
3832 let Inst{11-4} = 0b11111110;
3833 let Inst{3-0} = Rd;
3843 let Inst{11-8} = Rt2;
3849 let Inst{31-16} = 0xf3bf;
3850 let Inst{15-14} = 0b10;
3853 let Inst{11-8} = 0b1111;
3854 let Inst{7-4} = 0b0010;
3855 let Inst{3-0} = 0b1111;
3884 //===----------------------------------------------------------------------===//
3887 // address and save #0 in R0 for the non-longjmp case.
3895 // all of the callee-saved registers, which is exactly what we want.
3921 //===----------------------------------------------------------------------===//
3922 // Control-Flow Instructions
3941 let Inst{31-27} = 0b11110;
3942 let Inst{15-14} = 0b10;
3949 let Inst{25-16} = target{20-11};
3950 let Inst{10-0} = target{10-0};
3958 // available in both v8-M.Baseline and Thumb2 targets
3967 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3971 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3978 let Inst{31-20} = 0b111010001101;
3979 let Inst{19-16} = Rn;
3980 let Inst{15-5} = 0b11110000000;
3982 let Inst{3-0} = Rm;
3991 let Inst{31-20} = 0b111010001101;
3992 let Inst{19-16} = Rn;
3993 let Inst{15-5} = 0b11110000000;
3995 let Inst{3-0} = Rm;
4004 // a two-value operand where a dag node expects ", "two operands. :(
4009 let Inst{31-27} = 0b11110;
4010 let Inst{15-14} = 0b10;
4014 let Inst{25-22} = p;
4020 let Inst{21-16} = target{17-12};
4021 let Inst{10-0} = target{11-1};
4045 // 16-bit instruction.
4046 let Inst{31-16} = 0x0000;
4047 let Inst{15-8} = 0b10111111;
4051 let Inst{7-4} = cc;
4052 let Inst{3-0} = mask;
4057 // Branch and Exchange Jazelle -- for disassembly only
4058 // Rm = Inst{19-16}
4063 let Inst{31-27} = 0b11110;
4065 let Inst{25-20} = 0b111100;
4066 let Inst{19-16} = func;
4067 let Inst{15-0} = 0b1000111100000000;
4072 // Compare and branch on zero / non-zero
4082 let Inst{7-3} = target{4-0};
4083 let Inst{2-0} = Rn;
4094 let Inst{7-3} = target{4-0};
4095 let Inst{2-0} = Rn;
4112 let Inst{31-11} = 0b111100111010111110000;
4113 let Inst{10-9} = imod;
4115 let Inst{7-5} = iflags;
4116 let Inst{4-0} = mode;
4134 // Table A6-14 Change Processor State, and hint instructions
4138 let Inst{31-3} = 0b11110011101011111000000000000;
4139 let Inst{7-0} = imm;
4174 let Inst{31-20} = 0b111100111010;
4175 let Inst{19-16} = 0b1111;
4176 let Inst{15-8} = 0b10000000;
4177 let Inst{7-4} = 0b1111;
4178 let Inst{3-0} = opt;
4183 // Option = Inst{19-16}
4187 let Inst{31-27} = 0b11110;
4188 let Inst{26-20} = 0b1111111;
4189 let Inst{15-12} = 0b1000;
4192 let Inst{19-16} = opt;
4197 let Inst{31-27} = 0b11110;
4198 let Inst{26-20} = 0b1111000;
4199 let Inst{19-16} = 0b1111;
4200 let Inst{15-12} = 0b1000;
4201 let Inst{11-2} = 0b0000000000;
4202 let Inst{1-0} = opt;
4214 let Inst{31-25} = 0b1110100;
4215 let Inst{24-23} = Op;
4218 let Inst{20-16} = 0b01101;
4219 let Inst{15-5} = 0b11000000000;
4220 let Inst{4-0} = mode{4-0};
4246 let Inst{31-20} = op31_20{11-0};
4249 let Inst{19-16} = Rn;
4250 let Inst{15-0} = 0xc000;
4273 let Inst{31-8} = 0b111100111101111010001111;
4276 let Inst{7-0} = imm;
4280 // In the Thumb instruction set, MOVS{<c>}{<q>} PC, LR is a pseudo-instruction
4285 // ERET - Return from exception in Hypervisor mode.
4296 let Inst{31-20} = 0b111101111110;
4297 let Inst{19-16} = imm16{15-12};
4298 let Inst{15-12} = 0b1000;
4299 let Inst{11-0} = imm16{11-0};
4306 //===----------------------------------------------------------------------===//
4307 // Non-Instruction Patterns
4310 // 32-bit immediate using movw + movt.
4311 // This is a single pseudo instruction to make it re-materializable.
4360 // be expanded into two instructions late to allow if-conversion and
4376 //===----------------------------------------------------------------------===//
4377 // Coprocessor load/store -- for disassembly only
4382 let Inst{31-28} = op31_28;
4383 let Inst{27-25} = 0b110;
4398 let Inst{19-16} = addr{12-9};
4399 let Inst{15-12} = CRd;
4400 let Inst{11-8} = cop;
4401 let Inst{7-0} = addr{7-0};
4415 let Inst{19-16} = addr{12-9};
4416 let Inst{15-12} = CRd;
4417 let Inst{11-8} = cop;
4418 let Inst{7-0} = addr{7-0};
4434 let Inst{19-16} = addr;
4435 let Inst{15-12} = CRd;
4436 let Inst{11-8} = cop;
4437 let Inst{7-0} = offset{7-0};
4453 let Inst{19-16} = addr;
4454 let Inst{15-12} = CRd;
4455 let Inst{11-8} = cop;
4456 let Inst{7-0} = option;
4474 //===----------------------------------------------------------------------===//
4475 // Move between special register and ARM core register -- for disassembly only
4485 let Inst{31-12} = 0b11110011111011111000;
4486 let Inst{11-8} = Rd;
4487 let Inst{7-0} = 0b00000000;
4495 let Inst{31-12} = 0b11110011111111111000;
4496 let Inst{11-8} = Rd;
4497 let Inst{7-0} = 0b00000000;
4506 let Inst{31-21} = 0b11110011111;
4508 let Inst{19-16} = banked{3-0};
4509 let Inst{15-12} = 0b1000;
4510 let Inst{11-8} = Rd;
4511 let Inst{7-5} = 0b001;
4513 let Inst{3-0} = 0b0000;
4519 // This MRS has a mask field in bits 7-0 and can take more values than
4526 let Inst{31-12} = 0b11110011111011111000;
4527 let Inst{11-8} = Rd;
4528 let Inst{7-0} = SYSm;
4530 let Unpredictable{20-16} = 0b11111;
4541 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4549 let Inst{31-21} = 0b11110011100;
4551 let Inst{19-16} = Rn;
4552 let Inst{15-12} = 0b1000;
4553 let Inst{11-8} = mask{3-0};
4554 let Inst{7-0} = 0;
4565 let Inst{31-21} = 0b11110011100;
4567 let Inst{19-16} = Rn;
4568 let Inst{15-12} = 0b1000;
4569 let Inst{11-8} = banked{3-0};
4570 let Inst{7-5} = 0b001;
4572 let Inst{3-0} = 0b0000;
4585 let Inst{31-21} = 0b11110011100;
4587 let Inst{19-16} = Rn;
4588 let Inst{15-12} = 0b1000;
4589 let Inst{11-10} = SYSm{11-10};
4590 let Inst{9-8} = 0b00;
4591 let Inst{7-0} = SYSm{7-0};
4595 let Unpredictable{9-8} = 0b11;
4599 //===----------------------------------------------------------------------===//
4607 let Inst{27-24} = 0b1110;
4618 let Inst{15-12} = Rt;
4619 let Inst{11-8} = cop;
4620 let Inst{23-21} = opc1;
4621 let Inst{7-5} = opc2;
4622 let Inst{3-0} = CRm;
4623 let Inst{19-16} = CRn;
4631 let Inst{27-24} = 0b1100;
4632 let Inst{23-21} = 0b010;
4641 let Inst{15-12} = Rt;
4642 let Inst{19-16} = Rt2;
4643 let Inst{11-8} = cop;
4644 let Inst{7-4} = opc1;
4645 let Inst{3-0} = CRm;
4719 //===----------------------------------------------------------------------===//
4728 let Inst{27-24} = 0b1110;
4737 let Inst{3-0} = CRm;
4739 let Inst{7-5} = opc2;
4740 let Inst{11-8} = cop;
4741 let Inst{15-12} = CRd;
4742 let Inst{19-16} = CRn;
4743 let Inst{23-20} = opc1;
4754 let Inst{27-24} = 0b1110;
4763 let Inst{3-0} = CRm;
4765 let Inst{7-5} = opc2;
4766 let Inst{11-8} = cop;
4767 let Inst{15-12} = CRd;
4768 let Inst{19-16} = CRn;
4769 let Inst{23-20} = opc1;
4784 //===----------------------------------------------------------------------===//
4795 let Inst{2-0} = 0b000;
4798 let Unpredictable{2-0} = 0b111;
4801 //===----------------------------------------------------------------------===//
4802 // ARMv8-M Security Extensions instructions
4817 let Inst{31-20} = 0b111010000100;
4818 let Inst{19-16} = Rn;
4819 let Inst{15-12} = 0b1111;
4820 let Inst{11-8} = Rt;
4821 let Inst{7-6} = at;
4822 let Inst{5-0} = 0b000000;
4824 let Unpredictable{5-0} = 0b111111;
4840 //===----------------------------------------------------------------------===//
4841 // Non-Instruction Patterns
4919 //===----------------------------------------------------------------------===//
5093 // Non-predicable aliases of a predicable DSB: the predicate is (14, zero_reg) where
5098 // Armv8-R 'Data Full Barrier'
5104 // This gets lowered to a pair of 4-byte instructions
5108 // This gets lowered to a single 4-byte instructions
5166 // PUSH/POP aliases for STM/LDM
5173 def : t2InstAlias<"stm${p} $Rn, $regs",
5175 def : t2InstAlias<"stm${p} $Rn!, $regs",
5227 // STM w/o the .w suffix.
5228 def : t2InstAlias<"stm${p} $Rn, $regs",
5316 // Same for AND <--> BIC
5341 // And ORR <--> ORN
5354 // Likewise, "add Rd, t2_so_imm_neg" -> sub
5367 // Same for CMP <--> CMN via t2_so_imm_neg
5445 //===----------------------------------------------------------------------===//
5460 let Inst{31-16} = 0b1110100010011111;
5461 let Inst{15-14} = regs{15-14};
5463 let Inst{12-0} = regs{12-0};
5469 let Inst{31-27} = 0b11110;
5470 let Inst{15-14} = 0b11;
5489 let Inst{26-23} = b_label{3-0};
5490 let Inst{22-21} = 0b10;
5491 let Inst{20-16} = label{15-11};
5494 let Inst{10-1} = label{10-1};
5505 let Inst{26-23} = b_label{3-0};
5507 let Inst{21-18} = bcond{3-0};
5512 let Inst{10-1} = label{10-1};
5520 let Inst{26-23} = b_label{3-0};
5521 let Inst{22-20} = 0b110;
5522 let Inst{19-16} = Rn{3-0};
5523 let Inst{13-1} = 0b1000000000000;
5531 let Inst{26-23} = b_label{3-0};
5532 let Inst{22-16} = label{17-11};
5535 let Inst{10-1} = label{10-1};
5543 let Inst{26-23} = b_label{3-0};
5544 let Inst{22-20} = 0b111;
5545 let Inst{19-16} = Rn{3-0};
5546 let Inst{13-1} = 0b1000000000000;
5551 let Inst{31-23} = 0b111100000;
5552 let Inst{15-14} = 0b11;
5564 let Inst{22-20} = 0b100;
5565 let Inst{19-16} = Rn{3-0};
5566 let Inst{13-12} = 0b00;
5568 let Inst{10-1} = label{10-1};
5577 let Inst{22-20} = 0b100;
5578 let Inst{19-16} = Rn{3-0};
5579 let Inst{13-1} = 0b1000000000000;
5587 let Inst{22-16} = 0b0001111;
5588 let Inst{13-12} = 0b00;
5590 let Inst{10-1} = label{10-1};
5598 let Inst{22-16} = 0b0101111;
5599 let Inst{13-12} = 0b00;
5601 let Inst{10-1} = label{10-1};
5623 // will be created post-ISel from a llvm.test.start.loop.iterations. This
5665 // t2LoopEnd - the branch half of a t2LoopDec/t2LoopEnd pair.
5692 let Inst{31-20} = 0b111010100101;
5693 let Inst{19-16} = Rn{3-0};
5694 let Inst{15-12} = opcode;
5695 let Inst{11-8} = Rd{3-0};
5696 let Inst{7-4} = fcond{3-0};
5697 let Inst{3-0} = Rm{3-0};
5710 return N->hasOneUse();
5731 def : T2Pat<(ARMcmov (i32 -1), (i32 0), cmovpred:$imm),
5735 def : T2Pat<(ARMcmov (i32 0), (i32 -1), cmovpred:$imm),
5746 defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
5782 let Inst{31-20} = 0b111110110110;
5783 let Inst{19-16} = Rn;
5784 let Inst{15-12} = 0b1111;
5785 let Inst{11-8} = Rd;
5786 let Inst{7-4} = 0b0000;
5787 let Inst{3-0} = Rm;
5797 let Inst{31-20} = 0b111110110101;
5798 let Inst{19-16} = Rn;
5799 let Inst{15-12} = Ra;
5800 let Inst{11-5} = 0b1111000;
5802 let Inst{3-0} = Rm;
5819 let Inst{31-8} = 0b111100111010111110000000;
5820 let Inst{7-0} = imm;
5822 let Unpredictable{19-16} = 0b1111;
5823 let Unpredictable{13-11} = 0b101;