Lines Matching +full:stm +full:- +full:base
1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
22 unsigned Imm = N->getZExtValue();
23 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
27 uint64_t Imm = N->getZExtValue();
35 return (uint32_t)-N->getZExtValue() < 8;
40 unsigned Value = -(unsigned)N->getZExtValue();
48 unsigned Value = -(unsigned)N->getZExtValue();
56 return ~((uint32_t)N->getZExtValue()) < 256;
60 unsigned Val = -N->getZExtValue();
68 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
72 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
73 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
77 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
78 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
86 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
112 // unsigned 8-bit, 2-scaled memory offset
191 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
204 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
220 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
228 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
236 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
248 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
260 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
272 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
286 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
297 //===----------------------------------------------------------------------===//
318 let Inst{9-8} = 0b11;
319 let Inst{7-0} = opc;
327 let Inst{7-4} = imm;
349 let Inst{9-8} = 0b10;
352 let Inst{7-0} = val;
359 let Inst{9-6} = 0b1010;
361 let Inst{5-0} = val;
368 let Inst{9-5} = 0b10010;
371 let Inst{2-0} = 0b000;
374 // Change Processor State is a system instruction -- for disassembly only.
384 let Inst{2-0} = iflags;
395 let Inst{6-3} = 0b1111; // Rm = pc
396 let Inst{2-0} = dst;
409 let Inst{10-8} = dst;
410 let Inst{7-0} = imm;
416 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
428 let Inst{6-0} = imm;
439 let Inst{6-0} = imm;
461 let Inst{6-3} = 0b1101;
462 let Inst{2-0} = Rdn{2-0};
473 let Inst{6-3} = Rm;
474 let Inst{2-0} = 0b101;
478 //===----------------------------------------------------------------------===//
488 let Inst{6-3} = Rm;
489 let Inst{2-0} = 0b000;
490 let Unpredictable{2-0} = 0b111;
496 let Inst{6-3} = Rm;
497 let Inst{2-0} = 0b100;
498 let Unpredictable{1-0} = 0b11;
516 // All calls clobber the non-callee saved registers. SP is marked as a use to
517 // prevent stack-pointer assignments that appear immediately before calls from
529 let Inst{25-16} = func{20-11};
532 let Inst{10-0} = func{10-0};
542 let Inst{25-16} = func{20-11};
545 let Inst{10-1} = func{10-1};
555 let Inst{6-3} = func;
556 let Inst{2-0} = 0b000;
564 // ARMv8-M Security Extensions
570 let Inst{6-3} = func;
571 let Inst{2-0} = 0b100;
572 let Unpredictable{1-0} = 0b11;
604 let Inst{10-0} = target;
629 // a two-value operand where a dag node expects two operands. :(
637 let Inst{11-8} = p;
638 let Inst{7-0} = target;
654 // Non-MachO version:
667 // If Inst{11-8} == 0b1111 then SEE SVC
672 let Inst{15-12} = 0b1101;
673 let Inst{11-8} = 0b1111;
674 let Inst{7-0} = imm;
684 //===----------------------------------------------------------------------===//
688 // PC-relative loads need to be matched first as constant pool accesses need to
689 // always be PC-relative. We do this using AddedComplexity, as the pattern is
699 let Inst{10-8} = Rt;
700 let Inst{7-0} = addr;
703 // SP-relative loads should be matched before standard immediate-offset loads as
712 let Inst{10-8} = Rt;
713 let Inst{7-0} = addr;
723 // Immediate-offset loads should be matched before register-offset loads as
725 // immediate offset field then fall back to register-offset if it doesn't.
731 // Register-offset loads are matched last.
795 let Inst{10-8} = Rt;
796 let Inst{7-0} = addr;
818 //===----------------------------------------------------------------------===//
822 // These require base address to be written back or one of the loaded regs.
830 let Inst{10-8} = Rn;
831 let Inst{7-0} = regs;
835 // Writeback happens iff the base register is not in the destination register
851 // There is no non-writeback version of STM for Thumb.
856 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
860 let Inst{10-8} = Rn;
861 let Inst{7-0} = regs;
878 let Inst{7-0} = regs{7-0};
888 let Inst{7-0} = regs{7-0};
891 //===----------------------------------------------------------------------===//
902 let Inst{5-3} = Rm;
903 let Inst{2-0} = Rn;
911 let Inst{5-3} = Rm;
912 let Inst{2-0} = Rd;
922 let Inst{5-3} = Rn;
923 let Inst{2-0} = Rd;
932 let Inst{8-6} = Rm;
933 let Inst{5-3} = Rn;
934 let Inst{2-0} = Rd;
942 let Inst{5-3} = Rm;
943 let Inst{2-0} = Rd;
953 let Inst{5-3} = Rm;
954 let Inst{2-0} = Rdn;
962 let Inst{10-8} = Rdn;
963 let Inst{7-0} = imm8;
982 let Inst{8-6} = imm3;
1004 /// These opcodes will be converted to the real non-S opcodes by
1046 let Inst{6-3} = Rm;
1047 let Inst{2-0} = Rdn{2-0};
1085 let Inst{10-6} = imm5;
1106 // Compare-to-zero still works out, just not the relationals
1130 let Inst{10-8} = Rn;
1131 let Inst{7-0} = imm8;
1148 let Inst{6-3} = Rm;
1149 let Inst{2-0} = Rn{2-0};
1170 let Inst{10-6} = imm5;
1188 let Inst{10-6} = imm5;
1207 let Inst{10-8} = Rd;
1208 let Inst{7-0} = imm8;
1215 // A7-73: MOV(2) - mov setting flag.
1226 let Inst{6-3} = Rm;
1227 let Inst{2-0} = Rd{2-0};
1235 let Inst{15-6} = 0b0000000000;
1236 let Inst{5-3} = Rm;
1237 let Inst{2-0} = Rd;
1250 let Inst{5-3} = Rn;
1251 let Inst{2-0} = Rd;
1326 let Inst{8-6} = imm3;
1358 /// These opcodes will be converted to the real non-S opcodes by
1403 // Sign-extend byte
1412 // Sign-extend short
1429 // A8.8.247 UDF - Undefined (Encoding T1)
1433 let Inst{15-12} = 0b1101;
1434 let Inst{11-8} = 0b1110;
1435 let Inst{7-0} = imm8;
1448 // Zero-extend byte
1457 // Zero-extend short
1465 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1473 // tLEApcrel - Load a pc-relative address into a register without offending the
1481 let Inst{10-8} = Rd;
1482 let Inst{7-0} = addr;
1495 // Thumb-1 doesn't have the TBB or TBH instructions, but we can synthesize them
1496 // and make use of the same compressed jump table format as Thumb-2.
1500 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,
1504 (ins tGPRwithpc:$base, tGPR:$index, i32imm:$jt, i32imm:$pclbl), 0,
1508 //===----------------------------------------------------------------------===//
1512 // __aeabi_read_tp preserves the registers r1-r3.
1521 //===----------------------------------------------------------------------===//
1526 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1533 // preserve all of the callee-saved registers, which is exactly what we want.
1544 // FIXME: Non-IOS version(s)
1554 // (Windows is Thumb2-only)
1562 //===----------------------------------------------------------------------===//
1563 // Non-Instruction Patterns
1602 // 32-bit immediate using mov/add with the 4 :lower0_7: to :upper8_15:
1604 // This is a single pseudo instruction to make it re-materializable.
1634 // zextload i1 -> zextload i8
1640 // extload from the stack -> word load from the stack, as it avoids having to
1641 // materialize the base in a separate register. This only works when a word
1643 // byte/halfword load would, i.e. when little-endian.
1651 // extload -> zextload
1659 // post-inc loads and stores
1661 // post-inc LDR -> LDM r0!, {r1}. The way operands are layed out in LDMs is
1662 // different to how ISel expects them for a post-inc load, so use a pseudo
1671 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
1738 // be expanded into two instructions late to allow if-conversion and
1747 // Pseudo-instruction for merged POP and return.
1786 //===----------------------------------
1787 // Atomic cmpxchg for -O0
1788 //===----------------------------------