Lines Matching +full:stm +full:- +full:base
1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
257 // VDUPLANE can produce a quad-register result from a double-register source,
313 // reinterprets the _register_ format - and in big-endian, the memory and
318 // whereas 'bitconvert' will map it to the high byte in big-endian mode,
324 // In little-endian, VECTOR_REG_CAST is often turned into bitconvert during
334 // Reject a match against bitconvert (aka ISD::BITCAST) if big-endian
335 return !(CurDAG->getDataLayout().isBigEndian() &&
336 N->getOpcode() == ISD::BITCAST);
339 //===----------------------------------------------------------------------===//
368 //===----------------------------------------------------------------------===//
372 // imm_neg_XFORM - Return the negation of an i32 immediate value.
374 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
377 // imm_not_XFORM - Return the complement of a i32 immediate value.
379 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
384 // asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1
386 return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N), MVT:: i32);
389 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
394 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
396 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
413 /// Split a 32-bit immediate into two 16 bit parts.
415 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
420 // Returns true if all low 16-bits are 0.
421 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
424 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
426 return !SDValue(N,0)->getValueType(0).isVector() &&
427 CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
430 // topbitsallzero - Return true if all bits except the lowest bit are known zero
432 return SDValue(N,0)->getValueType(0) == MVT::i32 &&
433 CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 31));
441 return N->hasOneUse();
446 return N->hasOneUse();
451 return N->hasOneUse();
454 // An 'fadd' node which checks for single non-hazardous use.
459 // An 'fsub' node which checks for single non-hazardous use.
466 return N->getFlags().hasAllowContract();
474 //===----------------------------------------------------------------------===//
478 // Extract D sub-registers of Q registers.
481 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),
486 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
491 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
496 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
500 // Extract S sub-registers of Q/D registers.
503 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N),
507 // Extract S sub-registers of Q/D registers containing a given f16/bf16 lane.
510 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue()/2, SDLoc(N),
516 return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32);
519 return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32);
522 return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32);
532 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
534 uint64_t EltVal = ARM_AM::decodeVMOVModImm(ConstVal->getZExtValue(), EltBits);
535 return (EltBits == N->getValueType(0).getScalarSizeInBits() && EltVal == 0x01);
539 //===----------------------------------------------------------------------===//
567 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
573 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
658 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
683 switch (N->getZExtValue()){
685 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
686 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
687 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
688 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
696 int32_t v = N->getZExtValue();
703 // Power-of-two operand for MVE VIDUP and friends, which encode
704 // {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively
753 // (asr or lsl). The 6-bit immediate encodes as:
756 // {4-0} imm5 shift amount.
812 // mod_imm: match a 32-bit immediate operand, which can be encoded into
813 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
814 // - "Modified Immediate Constants"). Within the MC layer we keep this
821 return ARM_AM::getSOImmVal(Imm) != -1;
835 return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
842 unsigned Value = -(unsigned)N->getZExtValue();
843 return Value && ARM_AM::getSOImmVal(Value) != -1;
848 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
850 if (Subtarget->useMovt())
857 /// imm0_1 predicate - Immediate in the range [0,1].
861 /// imm0_3 predicate - Immediate in the range [0,3].
865 /// imm0_7 predicate - Immediate in the range [0,7].
875 /// imm8_255 predicate - Immediate in the range [8,255].
883 /// imm8 predicate - Immediate is exactly 8.
889 /// imm16 predicate - Immediate is exactly 16.
895 /// imm32 predicate - Immediate is exactly 32.
903 /// imm1_7 predicate - Immediate in the range [1,7].
909 /// imm1_15 predicate - Immediate in the range [1,15].
915 /// imm1_31 predicate - Immediate in the range [1,31].
921 /// imm0_15 predicate - Immediate in the range [0,15].
931 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
939 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
947 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
955 /// imm0_239 predicate - Immediate in the range [0,239].
963 /// imm0_255 predicate - Immediate in the range [0,255].
969 // imm0_255_expr - For Thumb1 movs/adds - 8-bit immediate that can also reference
982 /// imm0_65535 - An immediate is in the range [0,65535].
990 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
992 return -Imm >= 0 && -Imm < 65536;
995 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
1019 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
1031 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
1040 return ARM::isBitFieldInvertedMask(N->getZExtValue());
1054 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
1059 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
1066 uint64_t Imm = N->getZExtValue();
1075 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
1097 // half-open interval, so the parameters <1,8> mean 1-7 inclusive
1113 // half-open interval, so the parameters <1,16> mean 1-15 inclusive
1120 // addrmode_imm12 := reg +/- imm12
1125 // 12-bit immediate operand. Note that instructions using this encode
1126 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
1132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1143 // ldst_so_reg := reg +/- reg shop imm
1153 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1156 // postidx_imm8 := +/- [0,255]
1159 // {8} 1 is imm8 is non-negative. 0 otherwise.
1160 // {7-0} [0,255] imm8 value.
1168 // postidx_imm8s4 := +/- [0,1020]
1171 // {8} 1 is imm8 is non-negative. 0 otherwise.
1172 // {7-0} [0,255] imm8 value, scaled by 4.
1181 // postidx_reg := +/- reg
1204 // When using this for assembly, it's always as a post-index offset.
1222 // addrmode3 := reg +/- reg
1223 // addrmode3 := reg +/- imm8
1231 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1245 // FIXME: parser method to handle +/- register.
1266 // addrmode5 := reg +/- imm8*4
1274 let MIOperandInfo = (ops GPR:$base, i32imm);
1285 // addrmode5fp16 := reg +/- imm8*2
1293 let MIOperandInfo = (ops GPR:$base, i32imm);
1330 // Base class for addrmode6 with specific alignment restrictions.
1350 // Special version of addrmode6 to handle 16-bit alignment encoding for
1361 // Special version of addrmode6 to handle 32-bit alignment encoding for
1372 // Special version of addrmode6 to handle 64-bit alignment encoding for
1383 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1394 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1405 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1406 // instructions, specifically VLD4-dup.
1417 // Base class for addrmode6dup with specific alignment restrictions.
1426 // VLD-dup instruction and checking the alignment is not specified.
1436 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1447 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1458 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1469 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1496 let MIOperandInfo = (ops GPR:$base);
1499 // t_addr_offset_none := reg [r0-r7]
1505 let MIOperandInfo = (ops tGPR:$base);
1539 //===----------------------------------------------------------------------===//
1543 //===----------------------------------------------------------------------===//
1547 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1553 // The register-immediate version is re-materializable. This is useful
1564 let Inst{19-16} = Rn;
1565 let Inst{15-12} = Rd;
1566 let Inst{11-0} = imm;
1578 let Inst{19-16} = Rn;
1579 let Inst{15-12} = Rd;
1580 let Inst{11-4} = 0b00000000;
1581 let Inst{3-0} = Rm;
1593 let Inst{19-16} = Rn;
1594 let Inst{15-12} = Rd;
1595 let Inst{11-5} = shift{11-5};
1597 let Inst{3-0} = shift{3-0};
1609 let Inst{19-16} = Rn;
1610 let Inst{15-12} = Rd;
1611 let Inst{11-8} = shift{11-8};
1613 let Inst{6-5} = shift{6-5};
1615 let Inst{3-0} = shift{3-0};
1619 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1626 // The register-immediate version is re-materializable. This is useful
1637 let Inst{19-16} = Rn;
1638 let Inst{15-12} = Rd;
1639 let Inst{11-0} = imm;
1649 let Inst{11-4} = 0b00000000;
1651 let Inst{3-0} = Rm;
1652 let Inst{15-12} = Rd;
1653 let Inst{19-16} = Rn;
1665 let Inst{19-16} = Rn;
1666 let Inst{15-12} = Rd;
1667 let Inst{11-5} = shift{11-5};
1669 let Inst{3-0} = shift{3-0};
1681 let Inst{19-16} = Rn;
1682 let Inst{15-12} = Rd;
1683 let Inst{11-8} = shift{11-8};
1685 let Inst{6-5} = shift{6-5};
1687 let Inst{3-0} = shift{3-0};
1691 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1693 /// These opcodes will be converted to the real non-S opcodes by
1726 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1752 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1768 let Inst{19-16} = Rn;
1769 let Inst{15-12} = 0b0000;
1770 let Inst{11-0} = imm;
1772 let Unpredictable{15-12} = 0b1111;
1783 let Inst{19-16} = Rn;
1784 let Inst{15-12} = 0b0000;
1785 let Inst{11-4} = 0b00000000;
1786 let Inst{3-0} = Rm;
1789 let Unpredictable{15-12} = 0b1111;
1800 let Inst{19-16} = Rn;
1801 let Inst{15-12} = 0b0000;
1802 let Inst{11-5} = shift{11-5};
1804 let Inst{3-0} = shift{3-0};
1806 let Unpredictable{15-12} = 0b1111;
1817 let Inst{19-16} = Rn;
1818 let Inst{15-12} = 0b0000;
1819 let Inst{11-8} = shift{11-8};
1821 let Inst{6-5} = shift{6-5};
1823 let Inst{3-0} = shift{3-0};
1825 let Unpredictable{15-12} = 0b1111;
1831 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1842 let Inst{19-16} = 0b1111;
1843 let Inst{15-12} = Rd;
1844 let Inst{11-10} = rot;
1845 let Inst{3-0} = Rm;
1853 let Inst{19-16} = 0b1111;
1854 let Inst{11-10} = rot;
1857 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1869 let Inst{19-16} = Rn;
1870 let Inst{15-12} = Rd;
1871 let Inst{11-10} = rot;
1872 let Inst{9-4} = 0b000111;
1873 let Inst{3-0} = Rm;
1882 let Inst{19-16} = Rn;
1883 let Inst{11-10} = rot;
1886 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1900 let Inst{15-12} = Rd;
1901 let Inst{19-16} = Rn;
1902 let Inst{11-0} = imm;
1912 let Inst{11-4} = 0b00000000;
1915 let Inst{3-0} = Rm;
1916 let Inst{15-12} = Rd;
1917 let Inst{19-16} = Rn;
1929 let Inst{19-16} = Rn;
1930 let Inst{15-12} = Rd;
1931 let Inst{11-5} = shift{11-5};
1933 let Inst{3-0} = shift{3-0};
1946 let Inst{19-16} = Rn;
1947 let Inst{15-12} = Rd;
1948 let Inst{11-8} = shift{11-8};
1950 let Inst{6-5} = shift{6-5};
1952 let Inst{3-0} = shift{3-0};
1957 /// AI1_rsc_irs - Define instructions and patterns for rsc
1970 let Inst{15-12} = Rd;
1971 let Inst{19-16} = Rn;
1972 let Inst{11-0} = imm;
1981 let Inst{11-4} = 0b00000000;
1983 let Inst{3-0} = Rm;
1984 let Inst{15-12} = Rd;
1985 let Inst{19-16} = Rn;
1996 let Inst{19-16} = Rn;
1997 let Inst{15-12} = Rd;
1998 let Inst{11-5} = shift{11-5};
2000 let Inst{3-0} = shift{3-0};
2011 let Inst{19-16} = Rn;
2012 let Inst{15-12} = Rd;
2013 let Inst{11-8} = shift{11-8};
2015 let Inst{6-5} = shift{6-5};
2017 let Inst{3-0} = shift{3-0};
2034 let Inst{19-16} = addr{16-13}; // Rn
2035 let Inst{15-12} = Rt;
2036 let Inst{11-0} = addr{11-0}; // imm12
2045 let Inst{19-16} = shift{16-13}; // Rn
2046 let Inst{15-12} = Rt;
2047 let Inst{11-0} = shift{11-0};
2065 let Inst{19-16} = addr{16-13}; // Rn
2066 let Inst{15-12} = Rt;
2067 let Inst{11-0} = addr{11-0}; // imm12
2077 let Inst{19-16} = shift{16-13}; // Rn
2078 let Inst{15-12} = Rt;
2079 let Inst{11-0} = shift{11-0};
2097 let Inst{19-16} = addr{16-13}; // Rn
2098 let Inst{15-12} = Rt;
2099 let Inst{11-0} = addr{11-0}; // imm12
2108 let Inst{19-16} = shift{16-13}; // Rn
2109 let Inst{15-12} = Rt;
2110 let Inst{11-0} = shift{11-0};
2126 let Inst{19-16} = addr{16-13}; // Rn
2127 let Inst{15-12} = Rt;
2128 let Inst{11-0} = addr{11-0}; // imm12
2138 let Inst{19-16} = shift{16-13}; // Rn
2139 let Inst{15-12} = Rt;
2140 let Inst{11-0} = shift{11-0};
2145 //===----------------------------------------------------------------------===//
2147 //===----------------------------------------------------------------------===//
2149 //===----------------------------------------------------------------------===//
2153 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
2162 /// A jumptable consisting of direct 32-bit addresses of the destination basic
2163 /// blocks (either absolute, or relative to the start of the jump-table in PIC
2164 /// mode). Used mostly in ARM and Thumb-1 modes.
2169 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
2175 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
2181 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
2205 let Inst{27-8} = 0b00110010000011110000;
2206 let Inst{7-0} = imm;
2230 let Inst{3-0} = Rm;
2231 let Inst{15-12} = Rd;
2232 let Inst{19-16} = Rn;
2233 let Inst{27-20} = 0b01101000;
2234 let Inst{7-4} = 0b1011;
2235 let Inst{11-8} = 0b1111;
2236 let Unpredictable{11-8} = 0b1111;
2239 // The 16-bit operand $val can be used by a debugger to store more information
2244 let Inst{3-0} = val{3-0};
2245 let Inst{19-8} = val{15-4};
2246 let Inst{27-20} = 0b00010010;
2247 let Inst{31-28} = 0xe; // AL
2248 let Inst{7-4} = 0b0111;
2256 let Inst{3-0} = val{3-0};
2257 let Inst{19-8} = val{15-4};
2258 let Inst{27-20} = 0b00010000;
2259 let Inst{31-28} = 0xe; // AL
2260 let Inst{7-4} = 0b0111;
2273 let Inst{31-28} = 0b1111;
2274 let Inst{27-20} = 0b00010000;
2275 let Inst{19-18} = imod;
2277 let Inst{16-9} = 0b00000000;
2278 let Inst{8-6} = iflags;
2280 let Inst{4-0} = mode;
2303 let Inst{31-26} = 0b111101;
2308 let Inst{21-20} = 0b01;
2309 let Inst{19-16} = addr{16-13}; // Rn
2310 let Inst{15-12} = 0b1111;
2311 let Inst{11-0} = addr{11-0}; // imm12
2319 let Inst{31-26} = 0b111101;
2324 let Inst{21-20} = 0b01;
2325 let Inst{19-16} = shift{16-13}; // Rn
2326 let Inst{15-12} = 0b1111;
2327 let Inst{11-0} = shift{11-0};
2339 let Inst{31-10} = 0b1111000100000001000000;
2341 let Inst{8-0} = 0;
2347 let Inst{27-4} = 0b001100100000111100001111;
2348 let Inst{3-0} = opt;
2351 // A8.8.247 UDF - Undefined (Encoding A1)
2355 let Inst{31-28} = 0b1110; // AL
2356 let Inst{27-25} = 0b011;
2357 let Inst{24-20} = 0b11111;
2358 let Inst{19-8} = imm16{15-4};
2359 let Inst{7-4} = 0b1111;
2360 let Inst{3-0} = imm16{3-0};
2376 * - In ARM: UDF #60896;
2377 * - In Thumb: UDF #254 followed by a branch-to-self.
2437 // LEApcrel - Load a pc-relative address into a register without offending the
2441 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2448 let Inst{27-25} = 0b001;
2450 let Inst{23-22} = label{13-12};
2453 let Inst{19-16} = 0b1111;
2454 let Inst{15-12} = Rd;
2455 let Inst{11-0} = label{11-0};
2467 //===----------------------------------------------------------------------===//
2476 let Inst{27-0} = 0b0001001011111111111100011110;
2483 let Inst{27-0} = 0b0001101000001111000000001110;
2487 // the user-space one).
2500 let Inst{31-4} = 0b1110000100101111111111110001;
2501 let Inst{3-0} = dst;
2508 let Inst{27-4} = 0b000100101111111111110001;
2509 let Inst{3-0} = dst;
2513 // SP is marked as a use to prevent stack-pointer assignments that appear
2516 // FIXME: Do we really need a non-predicated version? If so, it should
2524 let Inst{31-28} = 0b1110;
2526 let Inst{23-0} = func;
2535 let Inst{23-0} = func;
2543 let Inst{31-4} = 0b1110000100101111111111110011;
2544 let Inst{3-0} = func;
2555 let Inst{27-4} = 0b000100101111111111110011;
2556 let Inst{3-0} = func;
2600 // a two-value operand where a dag node expects two operands. :(
2606 let Inst{23-0} = target;
2651 let Inst{31-25} = 0b1111101;
2653 let Inst{23-0} = target{24-1};
2662 let Inst{23-20} = 0b0010;
2663 let Inst{19-8} = 0xfff;
2664 let Inst{7-4} = 0b0010;
2665 let Inst{3-0} = func;
2697 let Inst{23-4} = 0b01100000000000000111;
2698 let Inst{3-0} = opt;
2707 let Inst{23-0} = svc;
2716 let Inst{31-28} = 0b1111;
2717 let Inst{27-25} = 0b100;
2721 let Inst{19-16} = 0b1101; // SP
2722 let Inst{15-5} = 0b00000101000;
2723 let Inst{4-0} = mode;
2727 let Inst{24-23} = 0;
2730 let Inst{24-23} = 0;
2733 let Inst{24-23} = 0b10;
2736 let Inst{24-23} = 0b10;
2739 let Inst{24-23} = 0b01;
2742 let Inst{24-23} = 0b01;
2745 let Inst{24-23} = 0b11;
2748 let Inst{24-23} = 0b11;
2768 let Inst{31-28} = 0b1111;
2769 let Inst{27-25} = 0b100;
2773 let Inst{19-16} = Rn;
2774 let Inst{15-0} = 0xa00;
2778 let Inst{24-23} = 0;
2781 let Inst{24-23} = 0;
2784 let Inst{24-23} = 0b10;
2787 let Inst{24-23} = 0b10;
2790 let Inst{24-23} = 0b01;
2793 let Inst{24-23} = 0b01;
2796 let Inst{24-23} = 0b11;
2799 let Inst{24-23} = 0b11;
2812 let Inst{31-28} = 0b1110;
2813 let Unpredictable{31-28} = 0b1111;
2814 let Inst{27-24} = 0b0001;
2815 let Inst{23-20} = 0b0100;
2816 let Inst{19-8} = imm{15-4};
2817 let Inst{7-4} = 0b0111;
2818 let Inst{3-0} = imm{3-0};
2826 let Inst{23-0} = 0b011000000000000001101110;
2829 //===----------------------------------------------------------------------===//
2843 // Special LDR for loads from non-pc-relative constpools.
2852 let Inst{19-16} = 0b1111;
2853 let Inst{15-12} = Rt;
2854 let Inst{11-0} = addr{11-0}; // imm12
2898 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2902 let Inst{19-16} = addr{16-13};
2903 let Inst{11-0} = addr{11-0};
2909 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2913 let Inst{19-16} = addr{16-13};
2914 let Inst{11-0} = addr{11-0};
2923 "$addr.base = $Rn_wb", []> {
2925 // {11-0} imm12/Rm
2930 let Inst{19-16} = addr;
2931 let Inst{11-0} = offset{11-0};
2941 "$addr.base = $Rn_wb", []> {
2943 // {11-0} imm12/Rm
2948 let Inst{19-16} = addr;
2949 let Inst{11-0} = offset{11-0};
2967 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2971 let Inst{19-16} = addr{12-9}; // Rn
2972 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2973 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2979 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2985 let Inst{19-16} = addr;
2986 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2987 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3001 "$addr.base = $Rn_wb", []> {
3005 let Inst{19-16} = addr{12-9}; // Rn
3006 let Inst{11-8} = addr{7-4}; // imm7_4/zero
3007 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3014 "$addr.base = $Rn_wb", []> {
3019 let Inst{19-16} = addr;
3020 let Inst{11-8} = offset{7-4}; // imm7_4/zero
3021 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3033 "$addr.base = $Rn_wb", []> {
3035 // {11-0} imm12/Rm
3041 let Inst{19-16} = addr;
3042 let Inst{11-5} = offset{11-5};
3044 let Inst{3-0} = offset{3-0};
3052 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3054 // {11-0} imm12/Rm
3060 let Inst{19-16} = addr;
3061 let Inst{11-0} = offset{11-0};
3069 "$addr.base = $Rn_wb", []> {
3071 // {11-0} imm12/Rm
3077 let Inst{19-16} = addr;
3078 let Inst{11-5} = offset{11-5};
3080 let Inst{3-0} = offset{3-0};
3088 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3090 // {11-0} imm12/Rm
3096 let Inst{19-16} = addr;
3097 let Inst{11-0} = offset{11-0};
3105 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3109 let Inst{11-8} = offset{7-4};
3110 let Inst{3-0} = offset{3-0};
3115 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3119 let Inst{11-8} = 0;
3120 let Unpredictable{11-8} = 0b1111;
3121 let Inst{3-0} = Rm{3-0};
3179 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3183 let Inst{19-16} = addr{16-13}; // Rn
3184 let Inst{11-0} = addr{11-0}; // imm12
3192 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3196 let Inst{19-16} = addr{16-13}; // Rn
3197 let Inst{11-0} = addr{11-0};
3205 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3207 // {11-0} imm12/Rm
3212 let Inst{19-16} = addr;
3213 let Inst{11-0} = offset{11-0};
3223 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3225 // {11-0} imm12/Rm
3230 let Inst{19-16} = addr;
3231 let Inst{11-0} = offset{11-0};
3261 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
3263 // the address base and offset to be separate operands, not a single
3301 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
3305 let Inst{19-16} = addr{12-9}; // Rn
3306 let Inst{11-8} = addr{7-4}; // imm7_4/zero
3307 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3315 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
3323 let Inst{19-16} = addr;
3324 let Inst{11-8} = offset{7-4}; // imm7_4/zero
3325 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3334 "$addr.base = $Rn_wb", []> {
3338 let Inst{19-16} = addr{12-9}; // Rn
3339 let Inst{11-8} = addr{7-4}; // imm7_4/zero
3340 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3349 "$addr.base = $Rn_wb", []> {
3354 let Inst{19-16} = addr;
3355 let Inst{11-8} = offset{7-4}; // imm7_4/zero
3356 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3367 "$addr.base = $Rn_wb", []> {
3369 // {11-0} imm12/Rm
3375 let Inst{19-16} = addr;
3376 let Inst{11-5} = offset{11-5};
3378 let Inst{3-0} = offset{3-0};
3386 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3388 // {11-0} imm12/Rm
3394 let Inst{19-16} = addr;
3395 let Inst{11-0} = offset{11-0};
3408 "$addr.base = $Rn_wb", []> {
3410 // {11-0} imm12/Rm
3416 let Inst{19-16} = addr;
3417 let Inst{11-5} = offset{11-5};
3419 let Inst{3-0} = offset{3-0};
3427 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3429 // {11-0} imm12/Rm
3435 let Inst{19-16} = addr;
3436 let Inst{11-0} = offset{11-0};
3449 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3453 let Inst{11-8} = offset{7-4};
3454 let Inst{3-0} = offset{3-0};
3459 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3463 let Inst{11-8} = 0;
3464 let Inst{3-0} = Rm{3-0};
3478 //===----------------------------------------------------------------------===//
3490 let Inst{24-23} = 0b01; // Increment After
3499 let Inst{24-23} = 0b01; // Increment After
3510 let Inst{24-23} = 0b00; // Decrement After
3519 let Inst{24-23} = 0b00; // Decrement After
3530 let Inst{24-23} = 0b10; // Decrement Before
3539 let Inst{24-23} = 0b10; // Decrement Before
3550 let Inst{24-23} = 0b11; // Increment Before
3559 let Inst{24-23} = 0b11; // Increment Before
3575 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3596 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3601 //===----------------------------------------------------------------------===//
3611 let Inst{19-16} = 0b0000;
3612 let Inst{11-4} = 0b00000000;
3614 let Inst{3-0} = Rm;
3615 let Inst{15-12} = Rd;
3625 let Inst{11-4} = 0b00000000;
3627 let Inst{3-0} = Rm;
3628 let Inst{15-12} = Rd;
3638 let Inst{15-12} = Rd;
3639 let Inst{19-16} = 0b0000;
3640 let Inst{11-8} = src{11-8};
3642 let Inst{6-5} = src{6-5};
3644 let Inst{3-0} = src{3-0};
3654 let Inst{15-12} = Rd;
3655 let Inst{19-16} = 0b0000;
3656 let Inst{11-5} = src{11-5};
3658 let Inst{3-0} = src{3-0};
3669 let Inst{15-12} = Rd;
3670 let Inst{19-16} = 0b0000;
3671 let Inst{11-0} = imm;
3682 let Inst{15-12} = Rd;
3683 let Inst{11-0} = imm{11-0};
3684 let Inst{19-16} = imm{15-12};
3694 // This gets lowered to a single 4-byte instructions
3711 let Inst{15-12} = Rd;
3712 let Inst{11-0} = imm{11-0};
3713 let Inst{19-16} = imm{15-12};
3719 // This gets lowered to a single 4-byte instructions
3747 //===----------------------------------------------------------------------===//
3815 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3832 let Inst{27-21} = 0b0111101;
3833 let Inst{6-4} = 0b101;
3834 let Inst{20-16} = width;
3835 let Inst{15-12} = Rd;
3836 let Inst{11-7} = lsb;
3837 let Inst{3-0} = Rn;
3849 let Inst{27-21} = 0b0111111;
3850 let Inst{6-4} = 0b101;
3851 let Inst{20-16} = width;
3852 let Inst{15-12} = Rd;
3853 let Inst{11-7} = lsb;
3854 let Inst{3-0} = Rn;
3857 //===----------------------------------------------------------------------===//
3895 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3896 // The assume-no-carry-in form uses the negation of the input since add/sub
3912 // The with-carry-in form matches bitwise not instead of the negation.
3924 // (mul X, 2^n+1) -> (add (X << n), X)
3925 // (mul X, 2^n-1) -> (rsb X, (X << n))
3938 let Inst{27-20} = op27_20;
3939 let Inst{11-4} = op11_4;
3940 let Inst{19-16} = Rn;
3941 let Inst{15-12} = Rd;
3942 let Inst{3-0} = Rm;
3944 let Unpredictable{11-8} = 0b1111;
4057 let Inst{27-20} = 0b01111000;
4058 let Inst{15-12} = 0b1111;
4059 let Inst{7-4} = 0b0001;
4060 let Inst{19-16} = Rd;
4061 let Inst{11-8} = Rm;
4062 let Inst{3-0} = Rn;
4073 let Inst{27-20} = 0b01111000;
4074 let Inst{7-4} = 0b0001;
4075 let Inst{19-16} = Rd;
4076 let Inst{15-12} = Ra;
4077 let Inst{11-8} = Rm;
4078 let Inst{3-0} = Rn;
4090 let Inst{27-21} = 0b0110101;
4091 let Inst{5-4} = 0b01;
4092 let Inst{20-16} = sat_imm;
4093 let Inst{15-12} = Rd;
4094 let Inst{11-7} = sh{4-0};
4096 let Inst{3-0} = Rn;
4106 let Inst{27-20} = 0b01101010;
4107 let Inst{11-4} = 0b11110011;
4108 let Inst{15-12} = Rd;
4109 let Inst{19-16} = sat_imm;
4110 let Inst{3-0} = Rn;
4121 let Inst{27-21} = 0b0110111;
4122 let Inst{5-4} = 0b01;
4123 let Inst{15-12} = Rd;
4124 let Inst{11-7} = sh{4-0};
4126 let Inst{20-16} = sat_imm;
4127 let Inst{3-0} = Rn;
4137 let Inst{27-20} = 0b01101110;
4138 let Inst{11-4} = 0b11110011;
4139 let Inst{15-12} = Rd;
4140 let Inst{19-16} = sat_imm;
4141 let Inst{3-0} = Rn;
4174 //===----------------------------------------------------------------------===//
4199 let Inst{27-21} = 0b0111110;
4200 let Inst{6-0} = 0b0011111;
4201 let Inst{15-12} = Rd;
4202 let Inst{11-7} = imm{4-0}; // lsb
4203 let Inst{20-16} = imm{9-5}; // msb
4206 // A8.6.18 BFI - Bitfield insert (Encoding A1)
4216 let Inst{27-21} = 0b0111110;
4217 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
4218 let Inst{15-12} = Rd;
4219 let Inst{11-7} = imm{4-0}; // lsb
4220 let Inst{20-16} = imm{9-5}; // width
4221 let Inst{3-0} = Rn;
4230 let Inst{19-16} = 0b0000;
4231 let Inst{11-4} = 0b00000000;
4232 let Inst{15-12} = Rd;
4233 let Inst{3-0} = Rm;
4235 let Unpredictable{19-16} = 0b1111;
4244 let Inst{19-16} = 0b0000;
4245 let Inst{15-12} = Rd;
4246 let Inst{11-5} = shift{11-5};
4248 let Inst{3-0} = shift{3-0};
4250 let Unpredictable{19-16} = 0b1111;
4259 let Inst{19-16} = 0b0000;
4260 let Inst{15-12} = Rd;
4261 let Inst{11-8} = shift{11-8};
4263 let Inst{6-5} = shift{6-5};
4265 let Inst{3-0} = shift{3-0};
4267 let Unpredictable{19-16} = 0b1111;
4276 let Inst{19-16} = 0b0000;
4277 let Inst{15-12} = Rd;
4278 let Inst{11-0} = imm;
4285 //===----------------------------------------------------------------------===//
4294 let Inst{19-16} = Rd;
4295 let Inst{11-8} = Rm;
4296 let Inst{3-0} = Rn;
4305 let Inst{19-16} = RdHi;
4306 let Inst{15-12} = RdLo;
4307 let Inst{11-8} = Rm;
4308 let Inst{3-0} = Rn;
4317 let Inst{19-16} = RdHi;
4318 let Inst{15-12} = RdLo;
4319 let Inst{11-8} = Rm;
4320 let Inst{3-0} = Rn;
4333 let Inst{15-12} = 0b0000;
4334 let Unpredictable{15-12} = 0b1111;
4354 let Inst{15-12} = Ra;
4375 let Inst{19-16} = Rd;
4376 let Inst{15-12} = Ra;
4377 let Inst{11-8} = Rm;
4378 let Inst{3-0} = Rn;
4443 let Inst{19-16} = RdHi;
4444 let Inst{15-12} = RdLo;
4445 let Inst{11-8} = Rm;
4446 let Inst{3-0} = Rn;
4475 let Inst{15-12} = 0b1111;
4483 let Inst{15-12} = 0b1111;
4638 let Inst{27-23} = 0b01110;
4640 let Inst{21-20} = 0b00;
4641 let Inst{11-8} = Rm;
4646 let Inst{3-0} = Rn;
4652 let Inst{15-12} = 0b1111;
4653 let Inst{19-16} = Rd;
4660 let Inst{19-16} = Rd;
4661 let Inst{15-12} = Ra;
4668 let Inst{19-16} = RdHi;
4669 let Inst{15-12} = RdLo;
4741 //===----------------------------------------------------------------------===//
4742 // Division Instructions (ARMv7-A with virtualization extension)
4756 //===----------------------------------------------------------------------===//
4816 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4841 //===----------------------------------------------------------------------===//
4858 let Inst{31-28} = 0b1110;
4859 let Inst{27-23} = 0b00010;
4860 let Inst{22-21} = sz;
4862 let Inst{19-16} = Rn;
4863 let Inst{15-12} = Rd;
4864 let Inst{11-10} = 0b00;
4867 let Inst{7-4} = 0b0100;
4868 let Inst{3-0} = Rm;
4870 let Unpredictable{11-8} = 0b1101;
4880 //===----------------------------------------------------------------------===//
4889 let Inst{31-28} = 0b1111;
4890 let Inst{27-20} = 0b00010001;
4891 let Inst{19-16} = 0b0000;
4892 let Inst{15-10} = 0b000000;
4895 let Inst{7-4} = 0b0000;
4896 let Inst{3-0} = 0b0000;
4898 let Unpredictable{19-16} = 0b1111;
4899 let Unpredictable{15-10} = 0b111111;
4901 let Unpredictable{3-0} = 0b1111;
4904 //===----------------------------------------------------------------------===//
4911 // ARMcmpZ can re-use the above instruction definitions.
4921 // with zero. Usage of CMPri in these cases helps to replace cmp with S-versions of
4928 // CMN register-integer
4938 let Inst{19-16} = Rn;
4939 let Inst{15-12} = 0b0000;
4940 let Inst{11-0} = imm;
4942 let Unpredictable{15-12} = 0b1111;
4945 // CMN register-register/shift
4955 let Inst{19-16} = Rn;
4956 let Inst{15-12} = 0b0000;
4957 let Inst{11-4} = 0b00000000;
4958 let Inst{3-0} = Rm;
4960 let Unpredictable{15-12} = 0b1111;
4973 let Inst{19-16} = Rn;
4974 let Inst{15-12} = 0b0000;
4975 let Inst{11-5} = shift{11-5};
4977 let Inst{3-0} = shift{3-0};
4979 let Unpredictable{15-12} = 0b1111;
4992 let Inst{19-16} = Rn;
4993 let Inst{15-12} = 0b0000;
4994 let Inst{11-8} = shift{11-8};
4996 let Inst{6-5} = shift{6-5};
4998 let Inst{3-0} = shift{3-0};
5000 let Unpredictable{15-12} = 0b1111;
5101 //===----------------------------------------------------------------------===//
5140 let Inst{31-4} = 0xf57ff05;
5141 let Inst{3-0} = opt;
5148 let Inst{31-4} = 0xf57ff04;
5149 let Inst{3-0} = opt;
5157 let Inst{31-4} = 0xf57ff06;
5158 let Inst{3-0} = opt;
5164 let Inst{31-0} = 0xe320f012;
5170 // Armv8.5-A speculation barrier
5173 let Inst{31-0} = 0xf57ff070;
5205 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
5209 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
5213 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
5218 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
5223 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
5228 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
5232 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
5236 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
5240 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
5245 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
5250 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
5255 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
5332 let Inst{31-0} = 0b11110101011111111111000000011111;
5345 class acquiring_load<PatFrag base>
5346 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
5347 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
5355 class releasing_store<PatFrag base>
5356 : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr), [{
5357 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
5385 //===----------------------------------------------------------------------===//
5402 let Inst{3-0} = CRm;
5404 let Inst{7-5} = opc2;
5405 let Inst{11-8} = cop;
5406 let Inst{15-12} = CRd;
5407 let Inst{19-16} = CRn;
5408 let Inst{23-20} = opc1;
5419 let Inst{31-28} = 0b1111;
5427 let Inst{3-0} = CRm;
5429 let Inst{7-5} = opc2;
5430 let Inst{11-8} = cop;
5431 let Inst{15-12} = CRd;
5432 let Inst{19-16} = CRn;
5433 let Inst{23-20} = opc1;
5443 let Inst{27-25} = 0b110;
5450 let Inst{31-28} = 0b1111;
5451 let Inst{27-25} = 0b110;
5467 let Inst{19-16} = addr{12-9};
5468 let Inst{15-12} = CRd;
5469 let Inst{11-8} = cop;
5470 let Inst{7-0} = addr{7-0};
5483 let Inst{19-16} = addr{12-9};
5484 let Inst{15-12} = CRd;
5485 let Inst{11-8} = cop;
5486 let Inst{7-0} = addr{7-0};
5501 let Inst{19-16} = addr;
5502 let Inst{15-12} = CRd;
5503 let Inst{11-8} = cop;
5504 let Inst{7-0} = offset{7-0};
5520 let Inst{19-16} = addr;
5521 let Inst{15-12} = CRd;
5522 let Inst{11-8} = cop;
5523 let Inst{7-0} = option;
5539 let Inst{19-16} = addr{12-9};
5540 let Inst{15-12} = CRd;
5541 let Inst{11-8} = cop;
5542 let Inst{7-0} = addr{7-0};
5555 let Inst{19-16} = addr{12-9};
5556 let Inst{15-12} = CRd;
5557 let Inst{11-8} = cop;
5558 let Inst{7-0} = addr{7-0};
5573 let Inst{19-16} = addr;
5574 let Inst{15-12} = CRd;
5575 let Inst{11-8} = cop;
5576 let Inst{7-0} = offset{7-0};
5592 let Inst{19-16} = addr;
5593 let Inst{15-12} = CRd;
5594 let Inst{11-8} = cop;
5595 let Inst{7-0} = option;
5612 //===----------------------------------------------------------------------===//
5630 let Inst{15-12} = Rt;
5631 let Inst{11-8} = cop;
5632 let Inst{23-21} = opc1;
5633 let Inst{7-5} = opc2;
5634 let Inst{3-0} = CRm;
5635 let Inst{19-16} = CRn;
5666 let Inst{31-24} = 0b11111110;
5677 let Inst{15-12} = Rt;
5678 let Inst{11-8} = cop;
5679 let Inst{23-21} = opc1;
5680 let Inst{7-5} = opc2;
5681 let Inst{3-0} = CRm;
5682 let Inst{19-16} = CRn;
5715 let Inst{23-21} = 0b010;
5724 let Inst{15-12} = Rt;
5725 let Inst{19-16} = Rt2;
5726 let Inst{11-8} = cop;
5727 let Inst{7-4} = opc1;
5728 let Inst{3-0} = CRm;
5745 let Inst{31-28} = 0b1111;
5746 let Inst{23-21} = 0b010;
5755 let Inst{15-12} = Rt;
5756 let Inst{19-16} = Rt2;
5757 let Inst{11-8} = cop;
5758 let Inst{7-4} = opc1;
5759 let Inst{3-0} = CRm;
5774 //===----------------------------------------------------------------------===//
5782 let Inst{23-16} = 0b00001111;
5783 let Unpredictable{19-17} = 0b111;
5785 let Inst{15-12} = Rd;
5787 let Inst{11-0} = 0b000000000000;
5788 let Unpredictable{11-0} = 0b110100001111;
5799 let Inst{23-16} = 0b01001111;
5800 let Unpredictable{19-16} = 0b1111;
5802 let Inst{15-12} = Rd;
5804 let Inst{11-0} = 0b000000000000;
5805 let Unpredictable{11-0} = 0b110100001111;
5818 let Inst{21-20} = 0b00;
5819 let Inst{19-16} = banked{3-0};
5820 let Inst{15-12} = Rd;
5821 let Inst{11-9} = 0b001;
5823 let Inst{7-0} = 0b00000000;
5831 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5841 let Inst{21-20} = 0b10;
5842 let Inst{19-16} = mask{3-0};
5843 let Inst{15-12} = 0b1111;
5844 let Inst{11-4} = 0b00000000;
5845 let Inst{3-0} = Rn;
5856 let Inst{21-20} = 0b10;
5857 let Inst{19-16} = mask{3-0};
5858 let Inst{15-12} = 0b1111;
5859 let Inst{11-0} = imm;
5872 let Inst{21-20} = 0b10;
5873 let Inst{19-16} = banked{3-0};
5874 let Inst{15-12} = 0b1111;
5875 let Inst{11-9} = 0b001;
5877 let Inst{7-4} = 0b0000;
5878 let Inst{3-0} = Rn;
5900 //===----------------------------------------------------------------------===//
5904 // __aeabi_read_tp preserves the registers r1-r3.
5924 //===----------------------------------------------------------------------===//
5927 // address and save #0 in R0 for the non-longjmp case.
5935 // all of the callee-saved registers, which is exactly what we want.
5938 // These are pseudo-instructions and are lowered to individual MC-insts, so
5962 // FIXME: Non-IOS version(s)
5975 // eh.sjlj.dispatchsetup pseudo-instruction.
5983 //===----------------------------------------------------------------------===//
5984 // Non-Instruction Patterns
6002 // 32-bit immediate using two piece mod_imms or movw + movt.
6075 // TODO: add,sub,and, 3-instr forms?
6096 // zextload i1 -> zextload i8
6100 // extload -> zextload
6155 // Pre-v7 uses MCR for synchronization barriers.
6201 //===----------------------------------------------------------------------===//
6207 //===----------------------------------------------------------------------===//
6213 //===----------------------------------------------------------------------===//
6219 //===----------------------------------------------------------------------===//
6225 //===----------------------------------------------------------------------===//
6231 //===----------------------------------------------------------------------===//
6237 //===----------------------------------------------------------------------===//
6247 // Armv8-R 'Data Full Barrier'
6258 def : MnemonicAlias<"stmia", "stm">;
6259 def : MnemonicAlias<"stmea", "stm">;
6270 // PUSH/POP aliases for STM/LDM
6352 // Same for AND <--> BIC
6366 // Likewise, "add Rd, mod_imm_neg" -> sub
6371 // Likewise, "sub Rd, mod_imm_neg" -> add
6387 // Same for CMP <--> CMN via mod_imm_neg
6433 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
6438 // the instruction definitions need difference constraints pre-v6.
6439 // Use these aliases for the assembly parsing on pre-v6.
6472 // This gets lowered to a pair of 4-byte instructions
6476 // This gets lowered to a single 4-byte instructions
6482 //===----------------------------------
6483 // Atomic cmpxchg for -O0
6484 //===----------------------------------
6486 // The fast register allocator used during -O0 inserts spills to cover any VRegs
6492 // post-regalloc) path for -O0 compilations. Fortunately this path can be
6517 //===----------------------------------------------------------------------===//
6519 //===----------------------------------------------------------------------===//
6539 //===----------------------------------------------------------------------===//
6540 // Pseudo Instructions for use when early-clobber is defined and Greedy Register
6542 //===----------------------------------------------------------------------===//