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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
[all …]
H A Dqcom,qca8k-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
10 - Bjorn Andersson <andersson@kernel.org>
11 - Luo Jie <quic_luoj@quicinc.com>
18 include/dt-bindings/clock/qcom,qca8k-nsscc.h
19 include/dt-bindings/reset/qcom,qca8k-nsscc.h
24 - const: qcom,qca8084-nsscc
[all …]
H A Dqcom,ipq5018-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5018
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
17 include/dt-bindings/clock/qcom,ipq5018-gcc.h
18 include/dt-bindings/reset/qcom,ipq5018-gcc.h
22 const: qcom,gcc-ipq5018
26 - description: Board XO source
[all …]
H A Dqcom,ipq9574-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-gcc.h
19 include/dt-bindings/reset/qcom,ipq9574-gcc.h
23 const: qcom,ipq9574-gcc
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H A Dqcom,ipq9574-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
23 const: qcom,ipq9574-nsscc
[all …]
H A Dqcom,qcs8300-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
17 See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
21 const: qcom,qcs8300-gcc
25 - description: Board XO source
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H A Dqcom,glymur-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on Glymur SoC
10 - Taniya Das <taniya.das@oss.qualcomm.com>
16 See also: include/dt-bindings/clock/qcom,glymur-gcc.h
20 const: qcom,glymur-gcc
24 - description: Board XO source
25 - description: Board XO_A source
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H A Dqcom,ipq5332-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
17 include/dt-bindings/clock/qcom,gcc-ipq5332.h
18 include/dt-bindings/clock/qcom,gcc-ipq5424.h
23 - qcom,ipq5332-gcc
24 - qcom,ipq5424-gcc
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H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
17 include/dt-bindings/clock/qcom,sm6350-videocc.h
18 include/dt-bindings/clock/qcom,videocc-sc7180.h
19 include/dt-bindings/clock/qcom,videocc-sc7280.h
20 include/dt-bindings/clock/qcom,videocc-sdm845.h
21 include/dt-bindings/clock/qcom,videocc-sm8150.h
[all …]
/linux/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
[all …]
/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 tristate "ASPEED Reset Driver"
30 This enables the reset controller driver for AST2700.
33 bool "AR71xx Reset Driver" if COMPILE_TEST
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/linux/sound/soc/codecs/
H A Dcs35l56.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <sound/cs-amp-lib.h>
31 #include <sound/soc-dapm.h>
43 flush_work(&cs35l56->dsp_work); in cs35l56_wait_dsp_ready()
66 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0);
181 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs35l56_play_event()
186 dev_dbg(cs35l56->base.dev, "play: %d\n", event); in cs35l56_play_event()
191 return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, in cs35l56_play_event()
195 ret = regmap_read_poll_timeout(cs35l56->base.regmap, in cs35l56_play_event()
196 cs35l56->base.fw_reg->transducer_actual_ps, in cs35l56_play_event()
[all …]
/linux/arch/arm/mach-omap1/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
[all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dpci_reset.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Test that PCI reset works correctly by verifying that only the expected reset
5 # methods are supported and that after issuing the reset the ifindex of the
14 source $lib_dir/lib.sh
15 source $lib_dir/devlink_lib.sh
21 local bus=$(echo $DEVLINK_DEV | cut -d '/' -f 1)
22 local bdf=$(echo $DEVLINK_DEV | cut -d '/' -f 2)
26 log_test "pci reset"
30 if [ ! -f /sys/bus/pci/devices/$bdf/reset_method ]; then
31 check_err 1 "reset is not supported"
[all …]
/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dreset.c8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmediatek,mt8188-afe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8188-afe
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
32 See dtschema reserved-memory/shared-dma-pool.yaml for details.
[all …]
H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - $ref: dai-common.yaml#
19 samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
21 samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
22 secondary FIFO, s/w reset control and internal mux for root clock
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-dimonoff-gateway-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include "imx8mn-var-som-symphony.dts"
13 compatible = "dimonoff,gateway-evk", "variscite,var-som-mx8mn",
18 * Source = BASE_PER_3V3 = SOM_3V3 (COM pin 49).
20 reg_disp_3v3: regulator-disp-3v3 {
21 compatible = "regulator-fixed";
22 regulator-name = "Display 3V3";
23 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dprm2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2012 Texas Instruments, Inc.
22 #include "prm-regbits-24xx.h"
25 * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
33 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
35 * reset source ID bit shifts (which is an OMAP SoC-independent
45 { -1, -1 },
49 * omap2xxx_prm_read_reset_sources - return the last SoC reset source
51 * Return a u32 representing the last reset sources of the SoC. The
52 * returned reset source bits are standardized across OMAP SoCs.
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dnxp,pcf8575.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
19 since the chip came out of reset (if any). The only reliable solution for
25 - maxim,max7328
26 - maxim,max7329
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