Lines Matching +full:reset +full:- +full:source

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on X1E80100
10   - Rajendra Nayak <quic_rjendra@quicinc.com>
16   See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h
21       - items:
22           - const: qcom,x1p42100-gcc
23           - const: qcom,x1e80100-gcc
24       - const: qcom,x1e80100-gcc
28       - description: Board XO source
29       - description: Sleep clock source
30       - description: PCIe 3 pipe clock
31       - description: PCIe 4 pipe clock
32       - description: PCIe 5 pipe clock
33       - description: PCIe 6a pipe clock
34       - description: PCIe 6b pipe clock
35       - description: USB4_0 QMPPHY clock source
36       - description: USB4_1 QMPPHY clock source
37       - description: USB4_2 QMPPHY clock source
38       - description: USB4_0 PHY DP0 GMUX clock source
39       - description: USB4_0 PHY DP1 GMUX clock source
40       - description: USB4_0 PHY PCIE PIPEGMUX clock source
41       - description: USB4_0 PHY PIPEGMUX clock source
42       - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43       - description: USB4_1 PHY DP0 GMUX 2 clock source
44       - description: USB4_1 PHY DP1 GMUX 2 clock source
45       - description: USB4_1 PHY PCIE PIPEGMUX clock source
46       - description: USB4_1 PHY PIPEGMUX clock source
47       - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48       - description: USB4_2 PHY DP0 GMUX 2 clock source
49       - description: USB4_2 PHY DP1 GMUX 2 clock source
50       - description: USB4_2 PHY PCIE PIPEGMUX clock source
51       - description: USB4_2 PHY PIPEGMUX clock source
52       - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
53       - description: USB4_0 PHY RX 0 clock source
54       - description: USB4_0 PHY RX 1 clock source
55       - description: USB4_1 PHY RX 0 clock source
56       - description: USB4_1 PHY RX 1 clock source
57       - description: USB4_2 PHY RX 0 clock source
58       - description: USB4_2 PHY RX 1 clock source
59       - description: USB4_0 PHY PCIE PIPE clock source
60       - description: USB4_0 PHY max PIPE clock source
61       - description: USB4_1 PHY PCIE PIPE clock source
62       - description: USB4_1 PHY max PIPE clock source
63       - description: USB4_2 PHY PCIE PIPE clock source
64       - description: USB4_2 PHY max PIPE clock source
66   power-domains:
72   - compatible
73   - clocks
74   - power-domains
75   - '#power-domain-cells'
78   - $ref: qcom,gcc.yaml#
83   - |
84     #include <dt-bindings/power/qcom,rpmhpd.h>
85     clock-controller@100000 {
86       compatible = "qcom,x1e80100-gcc";
125       power-domains = <&rpmhpd RPMHPD_CX>;
126       #clock-cells = <1>;
127       #reset-cells = <1>;
128       #power-domain-cells = <1>;