xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml (revision 75bfe7a0381e7fafd268e184b60b17574417a316) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Anusha Rao <quic_anusha@quicinc.com>
12
13description: |
14  Qualcomm networking sub system clock control module provides the clocks,
15  resets on IPQ9574
16
17  See also::
18    include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19    include/dt-bindings/reset/qcom,ipq9574-nsscc.h
20
21properties:
22  compatible:
23    const: qcom,ipq9574-nsscc
24
25  clocks:
26    items:
27      - description: Board XO source
28      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
30      - description: GCC GPLL0 OUT AUX clock source
31      - description: Uniphy0 NSS Rx clock source
32      - description: Uniphy0 NSS Tx clock source
33      - description: Uniphy1 NSS Rx clock source
34      - description: Uniphy1 NSS Tx clock source
35      - description: Uniphy2 NSS Rx clock source
36      - description: Uniphy2 NSS Tx clock source
37      - description: GCC NSSCC clock source
38
39  '#interconnect-cells':
40    const: 1
41
42  clock-names:
43    items:
44      - const: xo
45      - const: nss_1200
46      - const: ppe_353
47      - const: gpll0_out
48      - const: uniphy0_rx
49      - const: uniphy0_tx
50      - const: uniphy1_rx
51      - const: uniphy1_tx
52      - const: uniphy2_rx
53      - const: uniphy2_tx
54      - const: bus
55
56required:
57  - compatible
58  - clocks
59  - clock-names
60
61allOf:
62  - $ref: qcom,gcc.yaml#
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
69    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
70    clock-controller@39b00000 {
71      compatible = "qcom,ipq9574-nsscc";
72      reg = <0x39b00000 0x80000>;
73      clocks = <&xo_board_clk>,
74               <&cmn_pll NSS_1200MHZ_CLK>,
75               <&cmn_pll PPE_353MHZ_CLK>,
76               <&gcc GPLL0_OUT_AUX>,
77               <&uniphy 0>,
78               <&uniphy 1>,
79               <&uniphy 2>,
80               <&uniphy 3>,
81               <&uniphy 4>,
82               <&uniphy 5>,
83               <&gcc GCC_NSSCC_CLK>;
84      clock-names = "xo",
85                    "nss_1200",
86                    "ppe_353",
87                    "gpll0_out",
88                    "uniphy0_rx",
89                    "uniphy0_tx",
90                    "uniphy1_rx",
91                    "uniphy1_tx",
92                    "uniphy2_rx",
93                    "uniphy2_tx",
94                    "bus";
95      #clock-cells = <1>;
96      #reset-cells = <1>;
97    };
98...
99