Lines Matching +full:reset +full:- +full:source
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
92 #define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
97 /* Soft_POR_GEN register. The POR (Power On Reset) signal may be asserted
104 #define BBC_SPG_CPUALL 0x10 /* Reset all processors and reset
109 /* Soft_XIR_GEN register. The XIR (eXternally Initiated Reset) signal
118 /* POR Source register. One may identify the cause of the most recent
119 * reset by reading this register.
121 #define BBC_PSRC_SPG0 0x0001 /* CPU 0 reset via BBC_SPG register */
122 #define BBC_PSRC_SPG1 0x0002 /* CPU 1 reset via BBC_SPG register */
123 #define BBC_PSRC_SPG2 0x0004 /* CPU 2 reset via BBC_SPG register */
124 #define BBC_PSRC_SPG3 0x0008 /* CPU 3 reset via BBC_SPG register */
125 #define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
126 #define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
127 #define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
128 #define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
136 #define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
139 #define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
140 #define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
144 /* XIR Source register. The source of an XIR event sent to a processor may
158 /* Clock Synthesizers Control register. This register provides the big-bang
165 #define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
198 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
204 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
215 /* Keyboard Beep Counter register. There is a free-running counter inside