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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dresource-names.txt4 include a supplemental property for assigning names to each of the list
5 items. The names property consists of a list of strings in the same
6 order as the data in the resource property.
10 Resource Property Supplemental Names Property
11 ----------------- ---------------------------
12 reg reg-names
13 clocks clock-names
14 interrupts interrupt-names
18 The -names property must be used in conjunction with the normal resource
19 property. If not it will be ignored.
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H A Dexample-schema.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
45 # items is a list of possible values for the property. The number of
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bi
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dsrio-rmu.txt5 node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6 "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
10 - compatible
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
18 - reg
20 Value type: <prop-encoded-array>
21 Definition: A standard property. Specifies the physical address and
25 - fsl,liodn
26 Usage: optional-but-recommended (for devices with PAMU)
27 Value type: <prop-encoded-array>
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H A Dpamu.txt5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
14 A standard property. Utilized to describe the memory mapped
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
26 A standard property.
27 - #size-cells : <u32>
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H A Ddcsr.txt21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
30 Definition: A standard property. Defines the number of cells
33 - #size-cells
36 Definition: A standard property. Defines the number of cells
40 - range
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H A Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cell
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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp15xx-dkx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/mfd/st,stpmic1.h>
19 reg = <0xc0000000 0x20000000>;
22 reserved-memor
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H A Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixe
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H A Dstm32mp15xx-dhcor-drc-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
21 stdout-path = "serial0:115200n8";
25 compatible = "gpio-leds";
29 default-state = "off";
35 default-state = "off";
40 compatible = "regulator-fixe
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H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
28 reg = <0xc0000000 0x20000000>;
31 reserved-memor
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/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dfsl-sec4.txt3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
6 -Overview
7 -SEC 4 Node
8 -Job Ring Node
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
13 -Full Example
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
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H A Dfsl-sec6.txt4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
20 - compatible
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
28 Definition: A standard property. Define the 'ERA' of the SEC
31 - #address-cells
34 Definition: A standard property. Defines the number of cells
37 - #size-cells
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dqe.txt16 - compatible : should be "fsl,qe";
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18 - reg : offset and length of the device registers.
19 - bus-frequency : the clock frequency for QUICC Engine.
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
21 - fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
26 - fsl,firmware-phandle:
27 Usage: required only if there is no fsl,qe-firmware child node
31 The compatible property for the firmware node should say,
32 "fsl,qe-firmware".
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dqcom,spmi-vadc.txt3 - SPMI PMIC voltage ADC (VADC) provides interface to clients to read
4 voltage. The VADC is a 15-bit sigma-delta ADC.
5 - SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
6 voltage. The VADC is a 16-bit sigma-delta ADC.
10 - compatible:
13 Definition: Should contain "qcom,spmi-vadc".
14 Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
15 Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
16 Should contain "qcom,pms405-adc" for PMS405 PMIC
18 - reg:
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/freebsd/sys/contrib/device-tree/Bindings/x86/
H A Dce4100.txt2 ---------------------------
5 format: <vendor>,<chip>-<device>.
7 name in their compatible property because they first appeared in this
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
20 reg = <0x00>;
26 reg = <0x02>;
34 - device_type
37 - reg
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
21 controller node. This property is inherited, so it may be specified in an
23 "interrupts" property are always in reference to the node's interrupt parent.
25 The "interrupts-extended" property is a special form; useful when a node needs
27 the inherited one. Each entry in this property contains both the parent phandle
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
24 Array of names corresponding to clocks property.
28 - reg:
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung-fimc.txt2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
20 the clock-names property;
21 - clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-nsp-ax.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar Plus Ax stepping-specific bindings.
4 * Notable differences from B0+ are the secondary-boot-reg and
9 secondary-boot-reg = <0xffff042c>;
13 /delete-property/ dma-coherent;
17 /delete-property/ dma-coherent;
21 /delete-property/ dma-coherent;
25 /delete-property/ dma-coherent;
29 /delete-property/ dma-coherent;
33 /delete-property/ dma-coherent;
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC.
9 "sifive,fu740-c000-i2c", "sifive,i2c0"
11 FU740-C000 SoC.
12 Please refer to sifive-blocks-ip-versioning.txt for
14 - reg : bus address start and address range size of device
15 - clocks : handle to the controller clock; see the note below.
16 Mutually exclusive with opencores,ip-clock-frequency
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/freebsd/sys/dev/nvmem/
H A Dnvmem.c1 /*-
46 if (!OF_hasprop(node, "nvmem-cells") || in nvmem_get_cell_node()
47 !OF_hasprop(node, "nvmem-cell-names")) in nvmem_get_cell_node()
50 ncell = OF_getencprop_alloc_multi(node, "nvmem-cells", sizeof(*p_cell), (void **)&p_cell); in nvmem_get_cell_node()
73 uint32_t reg[2]; in nvmem_get_cell_len() local
76 rv = ofw_bus_find_string_index(node, "nvmem-cell-names", name, &idx); in nvmem_get_cell_len()
84 if (OF_getencprop(cell_node, "reg", reg, sizeof(reg)) != sizeof(reg)) { in nvmem_get_cell_len()
86 printf("nvmem_get_cell_len: Cannot parse reg property of cell %s\n", in nvmem_get_cell_len()
91 return (reg[1]); in nvmem_get_cell_len()
99 uint32_t reg[2]; in nvmem_read_cell_by_idx() local
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dmarvell-nand.txt4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
15 - #size-cells: shall be set to 0.
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