1*c66ec88fSEmmanuel VadotCE4100 Device Tree Bindings 2*c66ec88fSEmmanuel Vadot--------------------------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe CE4100 SoC uses for in core peripherals the following compatible 5*c66ec88fSEmmanuel Vadotformat: <vendor>,<chip>-<device>. 6*c66ec88fSEmmanuel VadotMany of the "generic" devices like HPET or IO APIC have the ce4100 7*c66ec88fSEmmanuel Vadotname in their compatible property because they first appeared in this 8*c66ec88fSEmmanuel VadotSoC. 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel VadotThe CPU nodes 11*c66ec88fSEmmanuel Vadot------------- 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot cpus { 14*c66ec88fSEmmanuel Vadot #address-cells = <1>; 15*c66ec88fSEmmanuel Vadot #size-cells = <0>; 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadot cpu@0 { 18*c66ec88fSEmmanuel Vadot device_type = "cpu"; 19*c66ec88fSEmmanuel Vadot compatible = "intel,ce4100"; 20*c66ec88fSEmmanuel Vadot reg = <0x00>; 21*c66ec88fSEmmanuel Vadot }; 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot cpu@2 { 24*c66ec88fSEmmanuel Vadot device_type = "cpu"; 25*c66ec88fSEmmanuel Vadot compatible = "intel,ce4100"; 26*c66ec88fSEmmanuel Vadot reg = <0x02>; 27*c66ec88fSEmmanuel Vadot }; 28*c66ec88fSEmmanuel Vadot }; 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel VadotA "cpu" node describes one logical processor (hardware thread). 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel VadotRequired properties: 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel Vadot- device_type 35*c66ec88fSEmmanuel Vadot Device type, must be "cpu". 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel Vadot- reg 38*c66ec88fSEmmanuel Vadot Local APIC ID, the unique number assigned to each processor by 39*c66ec88fSEmmanuel Vadot system hardware. 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel VadotThe SoC node 42*c66ec88fSEmmanuel Vadot------------ 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel VadotThis node describes the in-core peripherals. Required property: 45*c66ec88fSEmmanuel Vadot compatible = "intel,ce4100-cp"; 46*c66ec88fSEmmanuel Vadot 47*c66ec88fSEmmanuel VadotThe PCI node 48*c66ec88fSEmmanuel Vadot------------ 49*c66ec88fSEmmanuel VadotThis node describes the PCI bus on the SoC. Its property should be 50*c66ec88fSEmmanuel Vadot compatible = "intel,ce4100-pci", "pci"; 51*c66ec88fSEmmanuel Vadot 52*c66ec88fSEmmanuel VadotIf the OS is using the IO-APIC for interrupt routing then the reported 53*c66ec88fSEmmanuel Vadotinterrupt numbers for devices is no longer true. In order to obtain the 54*c66ec88fSEmmanuel Vadotcorrect interrupt number, the child node which represents the device has 55*c66ec88fSEmmanuel Vadotto contain the interrupt property. Besides the interrupt property it has 56*c66ec88fSEmmanuel Vadotto contain at least the reg property containing the PCI bus address and 57*c66ec88fSEmmanuel Vadotcompatible property according to "PCI Bus Binding Revision 2.1". 58